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■ Add-Subtract Instructions
Table I.2-1 Add-Subtract Instructions
Mnemonic
ADD
Rj, Ri
*ADD #s5, Ri
ADD
#u4, Ri
ADD2 #u4, Ris
ADDC Rj, Ri
ADDN Rj, Ri
*ADDN #s5, Ri
ADDN #u4, Ri
ADDN2 #u4, Ri
SUB
Rj, Ri
SUBC Rj, Ri
SUBN Rj, Ri
■ Compare Instructions
Table I.2-2 Compare Instructions
Mnemonic
CMP
Rj, Ri
*CMP #s5, Ri
CMP
#u4, Ri
CMP2 #u4, Ri
Type
OP
CYCLE
A
A6
1
C'
A4
1
C
A4
1
C
A5
1
A
A7
1
A
A2
1
C'
A0
1
C
A0
1
C
A1
1
A
AC
1
A
AD
1
A
AE
1
Type
OP
CYCLE
A
AA
1
C'
A8
1
C
A8
1
C
A9
1
NZVC
Operation
→
CCCC
Ri + Rj
Ri
→
CCCC
Ri + s5
Ri
→
CCCC
Ri + extu(i4)
→
CCCC
Ri + extu(i4)
→
CCCC
Ri + Rj + c
Ri
→
----
Ri + Rj
Ri
→
----
Ri + s5
Ri
→
----
Ri + extu(i4)
→
----
Ri + extu(i4)
→
CCCC
Ri - Rj
Ri
→
CCCC
Ri - Rj - c
Ri
→
----
Ri - Rj
Ri
NZVC
Operation
CCCC
Ri + Rj
CCCC
Ri + s5
CCCC
Ri + extu(i4)
CCCC
Ri + extu(i4)
APPENDIX I Instruction Lists
Remarks
The assembler treats the
highest-order bit as the sign.
Ri
Zero extension
Ri
Minus extension
Addition with carry
The assembler treats the
highest-order bit as the sign.
Ri
Zero extension
Ri
Minus extension
Addition with carry
Remarks
The assembler treats the
highest-order bit as the sign.
Zero extension
Minus extension
705
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