PCM AUDIO INTERFACE
3.1 PCM INPUT CLOCK DIAGRAM
PCLK
External Clock
S3C2416 PCM is able to select clock either PCLK or External Clock. Refer figure 25-3. To enable clock gating,
please refer to the SYSCON part(SCLKCON, PCLKCON).
25-4
PCM
PCM
SOURCE_
CLK
CTL_SERCLK_SEL
Figure 25-3. Input Clock Diagram for PCM
Clock Divider
1/2(SCLK_DIV+1)
(1/2~1/1024
even number)
1/(SYNC_DIV+1)
(1/16~1/512)
S3C2416X RISC MICROPROCESSOR
PCM_SCLK
PCM_FSYNC
PCM_CDCLK