Mobile Dram Control Register - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR
3.4

MOBILE DRAM CONTROL REGISTER

Register
BANKCON1
BANKCON
BUSY [31]
*
DQSInDLL [30:28]
Reserved [27:26]
Reserved [25:8]
BStop
WBUF
AP
PWRDN
Reserved [3:2]
INIT [1:0]
Address R/W
0x48000004 R/W
Bit
DRAM controller status bit (read only)
0 = IDLE
1 = BUSY
DQSIn Delay selection
Should be set '3'
Should be '1'
Should be '1'
Read Burst stop control
0 = Not support Read Burst Stop
[7]
1 = Support Read Burst Stop
Note: This function is only valid in mDDR interface.
Write buffer control
0 = Disable
[6] 1 = Enable
Note: Disabling the write buffer will flush any stored values to the
external DRAM memory.
Auto pre-charge control
0 = Enable auto pre-charge
[5] 1 = Disable auto pre-charge
Note: If PWRDN is enabled, then AP=0 provides pre-charge power
down and AP=1 provides active power down.
0 = Not support DRAM power down control
[4]
1 = Support DRAM power down control
Reserved
DRAM initialization control
00 = Normal operation
01 = Issue PALL command
10 = Issue MRS command
11 = Issue EMRS command
Description
Mobile DRAM control register
Description
MOBILE DRAM CONTROLLER
Reset Value
0x4400_0040
Initial State
0b
100b
01b
0
0b
1b
0b
0b
00b
00b
6-9