Samsung S3C2416 User Manual page 440

HS_SPI CONTROLLER
Register
MODE_CFG(Ch0)
MODE_CFG
Ch_tran_size
Trailing Count
BUS transfer size
RxTrigger
TxTrigger
reserved
RxDMA On
TxDMA On
DMA transfer
** Channel Transfer size must be smaller than Bus Transfer size or the same as.
19-8
Address R/W
0x52000008 R/W
Bit
[30:29] 00 = Byte
01 = Halfword
10 = Word
11 = Reserved
[28:19] Count value from writing the last data in RX FIFO to flush
trailing bytes in FIFO
00 = Byte
01 = Halfword
[18:17]
10 = Word
11 = Reserved
[16:11] Rx FIFO trigger level in INT mode.
Trigger level is from 0 to 63. The value means byte number in
RX FIFO
[10:5] Tx FIFO trigger level in INT mode
Trigger level is from 0 to 63. The value means byte number in
TX FIFO
[4:3]
−
[2] DMA mode on/off
0 = DMA mode off
1 = DMA mode on
[1] DMA mode on/off
0 = DMA mode off
1 = DMA mode on
[0] DMA transfer type, single or 4 bust.
0 = Single
1 = 4 burst
DMA transfer size should be set as the same size in DMA as it
in HS_SPI.
Description
HS_SPI FIFO control register
Description
S3C2416X RISC MICROPROCESSOR
Reset Value
Initial State
0x0
2'b0
10'b0
2'b0
6'b0
6'b0
−
1'b0
1'b0
1'b0