Samsung S3C2416 User Manual page 360

16/32-bit risc
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USB2.0 DEVICE
SSR
Bit
SDE
[3]
HFRM
[2]
HFSUSP
[1]
HFRES
[0]
16-14
R/W
R/C
Speed Detection End.
SDE is set by the core when the HS Detect Handshake
process is ended.
R/C
Host Forced Resume.
HFRM is set by the core in suspend state when host sends
resume signaling.
R/C
Host Forced Suspend
HFSUSP is set by the core when the SUSPEND signaling
from host is detected.
R/C
Host Forced Reset.
HFRES is set by the core when the RESET signaling from
host is detected.
S3C2416X RISC MICROPROCESSOR
Description
Initial State
0
0
0
0

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