System Control Register (Scr) - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

8.8 SYSTEM CONTROL REGISTER (SCR)

This register enables top-level control of the core. MCU should access this register for controls such as Power
saving mode enable/disable.
Register Address
SCR 0x4980_0020
SCR Bit
[31:15]
DTZIEN [14]
[13]
DIEN [12]
[11:9]
EIE [8]
SPDCEN [7]
SPDEN [6]
[5]
[4]
SPDC [3]
MFRM [2]
HSUSPE [1]
HRESE [0]
R/W
R/W System control register
R/W
− Reserved
R/W DMA Total Counter Zero Interrupt Enable
0 = Disable
1 = Enable
When set to 1, DMA total counter zero interrupt is
generated.
Reserved
−
R/W DUAL Interrupt Enable
0 = Disable
1 = Enable
When set to 1, Interrupt is activated until Interrupt source is
cleared.
Reserved
−
R/W Error Interrupt Enable
This bit must be set to 1 to enable error interrupt.
R/W Speed detection Control Enable
0 = Disable
1 = Enable
R/W Speed Detect End Interrupt Enable
When set to 1, Speed detection interrupt is generated.
− Reserved
Should be zero
−
R/W Speed detection Control
Software can reset Speed detection Logic through this bit.
This bit is used to control speed detection process in case of
System with a long initial time.
0 = Enable
1 = Disable
R/W Resume by MCU
If this bit is set, the suspended core generates a resume
signal. This bit is set when MCU writes 1. This bit is cleared
when MCU writes 0.
R/W Suspend Enable
When set to 1, core can respond to the suspend signaling
by USB host.
R/W Reset Enable
When set to 1, core can respond to the reset signaling by
USB host.
Description
Description
USB2.0 DEVICE
Reset Value
0x0
Initial State
0
0
0
0
0
0
0
0
0
0
16-15