Samsung S3C2416 User Manual page 7

Chapter 5
1 Overview ................................................................................................................................................... 5-1
2 Feature...................................................................................................................................................... 5-2
3 Block Diagram........................................................................................................................................... 5-3
3.1 Asynchronous Read ........................................................................................................................ 5-4
3.2 Asynchronous Burst Read............................................................................................................... 5-6
3.3 Synchronous Read/Synchronous Burst Read................................................................................. 5-7
3.4 Asynchronous Write ........................................................................................................................ 5-8
3.5 Synchronous Write/ Synchronous Burst Write ................................................................................ 5-10
3.6 Bus Turnaround............................................................................................................................... 5-11
4 Special Registers ...................................................................................................................................... 5-14
4.1 Bank Idle Cycle Control Registers 0-5 ............................................................................................ 5-14
4.2 Bank Read Wait State Control Registers 0-5.................................................................................. 5-14
4.3 Bank Write Wait State Control Registers 0-5 .................................................................................. 5-15
4.4 Bank Output Enable Assertion Delay Control Registers 0-5........................................................... 5-15
4.5 Bank Write Enable Assertion Delay Control Registers 0-5 ............................................................. 5-16
4.6 Bank Control Registers 0-5 ............................................................................................................. 5-17
4.7 Bank Onenand Type Selection Register ......................................................................................... 5-19
4.8 SMC Status Register ....................................................................................................................... 5-19
4.9 SMC Control Register...................................................................................................................... 5-20
Chapter 6
1 Overview ................................................................................................................................................... 6-1
2 Block Diagram........................................................................................................................................... 6-2
3 Mobile DRAM Initialization Sequence....................................................................................................... 6-3
3.1 Mobile DRAM(SDRAM or mobile DDR) Initialization Sequence..................................................... 6-3
3.2 DDR2 Initialization Sequence.......................................................................................................... 6-3
3.3 Mobile DRAM Configuration Register ............................................................................................. 6-8
3.4 Mobile DRAM Control Register ....................................................................................................... 6-9
3.5 Mobile DRAM Timming Control Register ........................................................................................ 6-10
3.6 Mobile DRAM (Extended ) Mode RegiSter Set Register................................................................. 6-11
3.7 Mobile DRAM Refresh Control Register ......................................................................................... 6-14
3.8 Mobile DRAM Write Buffer Time out Register................................................................................. 6-14
S3C2416X RISC MICROPROCESSOR
Table of Contents
Static Memory Controller (SMC)
Mobile DRAM Controller
(Continued)
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