Samsung S3C2416 User Manual page 142

STATIC MEMORY CONTROLLER
BurstLen
Read
SyncReadDev
BMRead
DRnCS
SMBLSPOL
MW
Reserved
WaitEn
WaitPol
RBLE
NOTE: Initial value of SMBCR0 is 0x303010 or 0x303000 according to OM value(See table 1-4), because the memory width,
MW, of the booting memory is determined by OM.
5-18
Bit
[11:10] Burst transfer length. Sets the number of sequential transfers
that the burst device supports for a read:
00 = 4-transfer burst.
10 = 16-transfer burst. 11 = Reserved
Synchronous access capable device connected. Access the
[9]
device using synchronous accesses for reads:
0 = Asynchronous device (default).
1 = Synchronous device.
[8] Burst mode read and asynchronous page mode:
0 = Nonburst reads from memory devices (default at reset).
1 = Burst mode reads from memory devices.
[7] 0 = No delay (defualt)
1 = Get the delay between ADDR signal and nCS signal.
The number of cycle is defined by DELAYnCS field of
SMBCRx.
This bit is applied only when nWAIT signal is used.
[6] Polarity of signal nBE:
0 = Signal is active LOW (default).
1 = Signal is active HIGH.
[5:4] Memory width:
00 = 8-bit.
10 = Reserved.
Defaults to different values at reset for each bank.
For SMBCR0, reset value is set according to OM. (See table
1-4)
[3] Reserved
[2] External memory controller wait signal enable:
0 = The SMC is not controlled by the external wait signal
(default at reset).
1 = The SMC looks for the external wait input signal, nWAIT.
[1] Polarity of the external wait input for activation:
0 = The nWAIT signal is active LOW (default at reset).
1 = The nWAIT signal is active HIGH.
[0] Read byte lane enable:
0 = nBE[1:0] all deasserted HIGH during system reads from
external memory. This is for 8-bit devices where the byte lane
enable is connected to the write enable pin so you must
deassert it during a read (default at reset). The nBE signals
act as write enables in this configuration.
1 = nBE[1:0] all asserted LOW during system reads from
external memory. This is for 16 or 32-bit devices where you
use the separate write enable signal, and you must hold the
byte lane selects asserted during a read. The nBE signal acts
as the write enable in this configuration.
S3C2416X RISC MICROPROCESSOR
Description
01 = 8-transfer burst.
01 = 16-bit.
11 = Reserved.
Initial State
0x0
0x0
0x0
0x0
0x0
See note in p5-
17
0x0
0x0
0x0
0x0