Force Event Register For Error Interrupt Status - Samsung S3C2416 User Manual

HSMMC CONTROLLER

5.32 FORCE EVENT REGISTER FOR ERROR INTERRUPT STATUS

Register Address
FEERR0 0X4AC00052
FEERR1 0X4A800052
The Force Event Register is not a physically implemented register. Rather, it is an address at which the Error
Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt
Status Register if the corresponding bit of the Error Interrupt Status Enable Register is set.
• Writing 1: set each bit of the Error Interrupt Status Register
• Writing 0: no effect
By setting this register, the Error Interrupt can be set in the Error Interrupt Status register. In order to generate
Note:
interrupt signal, both the Error Interrupt Status Enable and Error Interrupt Signal Enable shall be set.
Name Bit
[15:10] Reserved
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
20-70
R/W
WO Force Event Error Interrupt Register Error Interrupt
(Channel 0)
WO Force Event Error Interrupt Register Error Interrupt
(Channel 1)
Force Event for ADMA Error
1 = Interrupt is generated
0 = No Interrupt
Force Event for Auto CMD12 Error
1 = Interrupt is generated
0 = No Interrupt
Reserved
Force Event for Data End Bit Error
1 = Interrupt is generated
0 = No Interrupt
Force Event for Data CRC Error
1 = Interrupt is generated
0 = No Interrupt
Force Event for Data Timeout Error
1 = Interrupt is generated
0 = No Interrupt
Force Event for Command Index Error
1 = Interrupt is generated
0 = No Interrupt
Force Event for Command End Bit Error
1 = Interrupt is generated
0 = No Interrupt
Force Event for Command CRC Error
1 = Interrupt is generated
0 = No Interrupt
Force Event for Command Timeout Error
1 = Interrupt is generated
0 = No Interrupt
Description
Description
S3C2416X RISC MICROPROCESSOR
Reset Value
Initial Value
0x0000
0x0000
0x0
0
0
0
0
0
0
0
0
0
0