System Controller Status Registers (Wkupstat And Rststat) - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR
8.6

SYSTEM CONTROLLER STATUS REGISTERS (WKUPSTAT AND RSTSTAT)

Software must know the status of the system controller after wakeup or reset. WKUPSTAT and RSTSTAT
registers store the information.
Register
RSTSTAT 0x4C00_0068
WKUPSTAT 0x4C00_006C
After S3C2416 is re-set or woken-up, the following two registers store the source of the activation. The value of
RSTSTAT register is cleared by the other reset. If each bit has '1' value, resets or wakeup events are occurred.
The reset priority is as follows: nRESET > WDTRST > SLEEP > DEEP-STOP > SW Reset
RSTSTAT Bit
RESERVED [31:6]
SWRST [5]
DEEP-STOP [4]
SLEEP [3]
WDTRST [2]
RESERVED [1]
EXTRST [0]
WKUPSTAT register indicates that which source was used for changing system state into normal mode from idle,
stop and sleep mode. The value of WKUPSTAT register can be cleared by writing '1'.
WKUPSTAT
RESERVED
BATF
RTC_TICK
RESERVED
RTC
EINT
Address R/W
R
R/W
-
Reset by software (see SWRST register)
Wakeup from DEEP-STOP (ARM Reset only)
Wakeup from RTC_TICK, RTC_ALARM, EINT and battery fault
from power-down mode. (Reset by waking-up from SLEEP mode)
Reset by Watch-dog reset
-
External reset by nRESET pin
Bit
[31:6] -
Waked-up by BATT_FLT assertion. This field is valid when
[5]
PWRCFG[1:0] = 2'b01
[4] Waked-up by RTC tick
[3:2] -
[1] Waked-up by RTC alarm
[0] Waked-up by external interrupts
Description
Reset status register
Wake-up status register
Description
Description
SYSTEM CONTROLLER
Reset Value
0x0000_0001
0x0000_0000
Initial Value
0x0000_000
0
0
0
0
0
1
Initial Value
0x0000_000
0
0
0x0
0
0
2-35