Rx Fif0 Structure For Blc = 10 (24-Bits/Channel) - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR
The Data is aligned in the RX FIFO for 24-bits/channel BLC as shown
31
INVALID
INVALID
INVALID
INVALID
The RXCHPAUSE in the I2SCON register can stop the serial data reception on the I2SSDI.The reception is
stopped once the current Left/Right channel is received. If the control registers in the I2SCON Register (I2S
Control Register) and I2SMOD Register (I2S Mode Register) are to be reprogrammed then it is advisable to
disable the RX channel.
The Status of RX FIFO can be checked by checking the bits in the I2SFIC Register (I2S FIFO Control Register).
23-14
23
Figure 23-7. RX FIF0 Structure for BLC = 10 (24-bits/channel)
BLC = 10 (24-bits/channel)
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
S3C2416X RISC MICROPROCESSOR
0
LOC 0
LOC 1
LOC 2
LOC 3
LOC 4
LOC 5
LOC 6
LOC 7
LOC 8
LOC 9
LOC 10
LOC 11
LOC 12
LOC 13
LOC 14
LOC 15