Programming Guide; Initialization; Play Mode (Tx Mode) With Dma; Recording Mode (Rx Mode) With Dma - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

7 PROGRAMMING GUIDE

The IIS bus interface can be accessed either by the processor using programmed I/O instructions or by the DMA
controller.

7.1 INITIALIZATION

1. Before you use IIS bus interface, you have to configure GPIOs to IIS mode. And check signal's direction.
I2SLRCLK, I2SSCLK and I2SCDCLK is inout-type. The each of I2SSDI and I2SSDO is input and output.
2. Now then, you choose clock source. S3C2416 has four clock sources. Those are PCLK, divided EPLL clock
EPLLRefCLK and external codec. If you want to know more detail, refer Figure 23-2.

7.2 PLAY MODE (TX MODE) WITH DMA

1. TXFIFO is flushed before operation. If you don't distinguish Master/Slave mode from TX/RX mode, you must
study Master/Slave mode and TX/RX mode. Refer Master/Slave chapter.
2. To configure I2SMOD register and I2SPSR (IIS pre-scaler register) properly.
3. To operate system in stability, the internal TXFIFO should be almost full before transmission. First of all, DMA
starts because of that reason.
4. Basically, IIS bus doesn't support the interrupt. So, you can only check state by polling through accessing
SFR.
5. If TXFIFO is full, now then you make I2SACTIVE be asserted.

7.3 RECORDING MODE (RX MODE) WITH DMA

1. RXFIFO is flushed before operation. Also, if you don't distinguish between Master/Slave mode and TX/RX
mode, you must study Master/Slave mode and TX/RX mode. Refer Master/Slave chapter.
2. To configure I2SMOD register and I2SPSR (IIS pre-scaler register) properly.
3. To operate system in stability, the internal RXFIFO should have at least one data before DMA operation.
Because of that reason, you make I2SACTIVE be asserted.
4. Now then you check RXFIFO state by polling through accessing SFR.
5. If RXFIFO is not empty, let's start RXDMACTIVE.
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S3C2416X RISC MICROPROCESSOR