Samsung S3C2416 User Manual page 556

LCD CONTROLLER
8.1.6 Video Time Control 1 Register
Register
VIDTCON1 0x4C80000C
VIDTCON1
HBPD [23:16]
HFPD [15:8]
HSPW
8.1.7 VIDEO Time Control 2 Register
Register
VIDTCON2 0x4C800010
VIDTCON2
LINEVAL [21:11]
HOZVAL [10:0]
21-36
Address R/W
R/W Video time control 2 register
Bit
Horizontal back porch is the number of VCLK periods between
the edge of HSYNC and the start of active data.
(Period : HBPD +1)
Note: Set 0x10 for i80-System Interface
When the PNRMODE (VIDCON0 [14:13]) is set to serial format the
period becomes 3 times of HBPD value.
(If HBPD is set to '0' in serial mode, the period becomes 3-VLCK)
Horizontal front porch is the number of VCLK periods between the
end of active data and the edge of next HSYNC.
(Period : HFPD +1)
Note: When the PNRMODE(VIDCON0[14:13]) is set to serial format the
period of HFPD becomes 3 times of VCLK
(If HFPD is set to '0' in serial mode, the period becomes 3-VLCK)
[7:0] Horizontal sync pulse width determines the HSYNC pulse's level
width by counting the number of the VCLK.
(Period : HSPW +1)
Note: When the PNRMODE(VIDCON0[14:13]) is set to serial format the
period of HSPW becomes 3 times of VCLK
(If HSPW is set to '0' in serial mode, the period becomes 3-VLCK)
Address R/W
R/W Video time control 3 register
Bit
These bits determine the vertical size of display
These bits determine the horizontal size of display
S3C2416X RISC MICROPROCESSOR
Description
Description
Description
Description
Reset Value
0x0000_0000
Initial state
0000000
0x00
0x00
Reset Value
0x0000_0000
Initial state
0
0