IIC-BUS INTERFACE
17-8
START
Master Rx mode has been
configured.
Write slave address to
IICDS.
Write 0xB0 (M/R Start) to
IICSTAT.
The data of the IICDS (slave
address) is transmitted.
ACK period and then
interrupt is pending.
Stop?
N
Read a new data from
IICDS.
Clear pending bit to
resume.
SDA is shifted to IICDS.
Figure 17-7. Operations for Master/Receiver Mode
Y
Write 0x90 (M/R Stop) to
IICSTAT.
Clear pending bit .
Wait until the stop
condition takes effect.
END
S3C2416X RISC MICROPROCESSOR