Spare Area Ecc Status Register; 4-Bit Ecc Error Patten Register - Samsung S3C2416 User Manual

S3C2416 RISC MICROPROCESSOR
13.13

SPARE AREA ECC STATUS REGISTER

Register Address
NFSECC 0x4E00003C
NFSECC
Reserved
SECC0_1
SECC0_0
NOTE: The NAND flash controller generate NFSECC when read or write spare area data while the SpareECCLock
(NFCONT[6]) bit is '0' (Unlock).
13.14

4-BIT ECC ERROR PATTEN REGISTER

Register Address
NFMLCBITPT 0x4E000040
NFMLCBITPT
th
4 Error bit pattern
rd
3 Error bit pattern
nd
2 Error bit pattern
st
1 Error bit pattern
R/W
R NAND Flash ECC register for I/O [7:0]
Bit
[31:16] Reserved
[15:8] Spare area ECC1 Status for I/O[7:0]
[7:0] Spare area ECC0 Status for I/O[7:0]
R/W
R NAND Flash 4-bit ECC Error Pattern register for
data[7:0]
Bit
th
[31:24]
4 Error bit pattern
rd
[23:16]
3 Error bit pattern
nd
[15:8]
2 Error bit pattern
[7:0] st
1 Error bit pattern
Description
Description
Description
Description
NAND FLASH CONTROLLER
Reset Value
0xXXXXXX
Initial State
0xXXXX
0xXX
0xXX
Reset Value
0x00000000
Initial State
0x00
0x00
0x00
0x00
7-25