Samsung S3C2416 User Manual page 497

S3C2416X RISC MICROPROCESSOR
Name
STACMDIDXERR
CMDEBITERR
STACMDCRCERR
STACMDTOUTERR
Bit
Occurs when detecting one of following timeout conditions.
(1) Busy timeout for R1b,R5b type
(2) Busy timeout after Write CRC status
(3) Write CRC Status timeout
(4) Read Data timeout.
1 = Timeout
0 = No Error
[3]
Command Index Error
Occurs if a Command Index error occurs in the command
response.
1 = Error
0 = No Error
[2]
Command End Bit Error
Occurs when detecting that the end bit of a command response
is 0.
1 = End bit Error generated
0 = No Error
[1]
Command CRC Error
Command CRC Error is generated in two cases.
(1) If a response is returned and the Command Timeout Error
is set to 0 (indicating no timeout), this bit is set to 1 when
detecting a CRC error in the command response.
(2) The Host Controller detects a CMD line conflict by
monitoring the CMD line when a command is issued. If the Host
Controller drives the CMD line to 1 level, but detects 0 level on
the CMD line at the next SDCLK edge, then the Host Controller
shall abort the command (Stop driving CMD line) and set this bit
to 1. The Command Timeout Error shall also be set to 1 to
distinguish CMD line conflict.
1 = CRC Error generated
0 = No Error
[0]
Command Timeout Error
Occurs only if no response is returned within 64 SDCLK cycles
from the end bit of the command. If the Host Controller detects a
CMD line conflict, in which case Command CRC Error shall
also be set as shown in Table 33, this bit shall be set without
waiting for 64 SDCLK cycles because the command will be
aborted by the Host Controller.
1 = Timeout
0 = No Error
Description
HSMMC CONTROLLER
Initial Value
0
0
0
20-51