Samsung S3C2416 User Manual page 478

HSMMC CONTROLLER
Name Bit
BUFWTRDY [10]
RDTRANACT [9]
WTTRANACT [8]
20-32
Buffer Write Enable (ROC)
This status is used for non-DMA write transfers. The Host Controller
can implement multiple buffers to transfer data efficiently. This read
only flag indicates if space is available for write data. If this bit is 1,
data can be written to the buffer. A change of this bit from 1 to 0
occurs when all the block data is written to the buffer. A change of
this bit from 0 to 1 occurs when top of block data can be written to
the buffer and generates the Buffer Write Ready interrupt.
1 = Write enable
0 = Write disable
Read Transfer Active (ROC)
This status is used for detecting completion of a read transfer.
This bit is set to 1 for either of the following conditions:
(1) After the end bit of the read command.
(2) When writing a 1 to Continue Request in the Block Gap Control
register to restart a read transfer.
This bit is cleared to 0 for either of the following conditions::
(1) When the last data block as specified by block length is
transferred to the System.
(2) When all valid data blocks have been transferred to the System
and no current block transfers are being sent as a result of the Stop
At Block Gap Request being set to 1. A Transfer Complete
interrupt is generated when this bit changes to 0.
1 = Transferring data
0 = No valid data
Write Transfer Active (ROC)
This status indicates a write transfer is active. If this bit is 0, it means
no valid write data exists in the Host Controller.
This bit is set in either of the following cases:
(1) After the end bit of the write command.
(2) When writing a 1 to Continue Request in the Block Gap Control
register to restart a write transfer.
This bit is cleared in either of the following cases:
(1) After getting the CRC status of the last data block as specified by
the transfer count (Single and Multiple)
(2) After getting the CRC status of any block where data
transmission is about to be stopped by a Stop At Block Gap
Request.
During a write transaction, a Block Gap Event interrupt is
generated when this bit is changed to 0, as result of the Stop At
Block Gap Request being set. This status is useful for the Host
Driver in determining when to issue commands during write busy.
1 = Transferring data
0 = No valid data
S3C2416X RISC MICROPROCESSOR
Description Initial Value
0
0
0