Samsung S3C2416 User Manual page 592

S3C2416X RISC MICROPROCESSOR
The Data is aligned in the TX FIFO for 8-bits/channel or 16-bits/channel BLC as shown
31
23-10
BLC=00
BLC=01
23
RIGHT CHANNEL
Figure 23-4. TX FIFO Structure for BLC = 00 or BLC = 01
BLC=00
16 15
LEFT CHANNEL
S3C2416X RISC MICROPROCESSOR
BLC=01
7
0
LOC 0
LOC 1
LOC 2
LOC 3
LOC 4
LOC 5
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LOC 7
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LOC 9
LOC 10
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LOC 12
LOC 13
LOC 14
LOC 15