Normal Interrupt Signal Enable Register - Samsung S3C2416 User Manual

HSMMC CONTROLLER

5.22 NORMAL INTERRUPT SIGNAL ENABLE REGISTER

This register is used to select which interrupt status is indicated to the Host System as the interrupt. These status
bits all share the same1 bit interrupt line. Setting any of these bits to 1 enables interrupt generation.
Register
NORINTSIGEN0
NORINTSIGEN1
Name
ENSIGFIA3
ENSIGFIA2
ENSIGFIA1
ENSIGFIA0
ENSIGRWAIT
ENSIGCCS
ENSIGCARDINT
ENSIGCARDREM
ENSIGCARDNS
20-56
Address R/W
0X4AC00038 R/W
0X4A800038 R/W
Bit
[15]
Fixed to 0
The Host Driver shall control error interrupts using the Error
Interrupt Signal Enable register.
[14]
FIFO SD Address Pointer Interrupt 3 Signal Enable
1 = Enabled
0 = Masked
[13]
FIFO SD Address Pointer Interrupt 2 Signal Enable
1 = Enabled
0 = Masked
[12]
FIFO SD Address Pointer Interrupt 1 Signal Enable
1 = Enabled
0 = Masked
[11]
FIFO SD Address Pointer Interrupt 0 Signal Enable
1 = Enabled
0 = Masked
[10]
Read Wait Interrupt Signal Enable
1 = Enabled
0 = Masked
[9]
CCS Interrupt Signal Enable
Command Complete Signal Interrupt Status bit is for CE-ATA
interface mode.
1 = Enabled
0 = Masked
[8]
Card Interrupt Signal Enable
1 = Enabled
0 = Masked
[7]
Card Removal Signal Enable
1 = Enabled
0 = Masked
[6]
Card Insertion Signal Enable
1 = Enabled
0 = Masked
Description
Normal Interrupt Signal Enable Register
(Channel 0)
Normal Interrupt Signal Enable Register
(Channel 1)
Description
S3C2416X RISC MICROPROCESSOR
Reset Value
Initial Value
0x0
0x0
0
0
0
0
0
0
0
0
0
0