Demand/Handshake Mode Comparison - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

Demand/Handshake Mode Comparison

These are two different modes related to the protocol between XnXDREQ and XnXDACK. Figure 8-2 shows the
differences between these two modes i.e., Demand and Handshake modes.
At the end of one transfer (Single/Burst transfer), DMA checks the state of double-synched XnXDREQ.
3.1.2 Demand mode
• If XnXDREQ remains asserted, the next transfer starts immediately. Otherwise it waits for XnXDREQ to be
asserted.
3.1.3 Handshake mode
• If XnXDREQ is deasserted, DMA deasserts XnXDACK in 2cycles. Otherwise it waits until XnXDREQ is
deasserted.
Caution: XnXDREQ has to be asserted (low) only after the deassertion (high) of XnXDACK.
XSCLK
Demand Mode
XnXDREQ
XnXDACK
Handshake Mode
XnXDREQ
XnXDACK
−
1st Transfer
Double
synch
BUS Acquisiton
Figure 8-2. Demand/Handshake Mode Comparison
Related to the Protocol between XnXDREQ and XnXDACK
2cycles
Read Write
Actual Transfer
Read Write
2cycles
DMA CONTROLLER
2nd Transfer
Read Write
Double
synch
2cycles
8-5