Iis Fifo Control Register (Iisfic); Iis Prescaler Control Register (Iispsr) - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

8.3 IIS FIFO CONTROL REGISTER (IISFIC)

Register
IISFIC
IISFIC
[31:29]
FTX2CNT [28:24]
[23:21]
FTX1CNT [20:16]
TFLUSH
[14:13]
FTX0CNT
RFLUSH
FRXCNT
NOTE: Tx FIFOs, Rx FIFO has 32-bit width and 16 depth structure, so FIFO data count value ranges from 0 to 16.

8.4 IIS PRESCALER CONTROL REGISTER (IISPSR)

Register
IISPSR
IISPSR
[31:16]
PSRAEN
PSVALA
23-20
Address
0x55000008 IIS interface FIFO control register
Bit R/W
R/W Reserved. Program to zero.
R TX FIFO2 data count. (0 ~ 16)
R/W Reserved. Program to zero.
R TX FIFO1 data count. (0~16)
[15] R/W TX FIFO flush command.
0 = No flush
1 = Flush
R/W Reserved. Program to zero.
[12:8] R TX FIFO0 data count. (0~16)
[7] R/W RX FIFO flush command.
0 = No flush
1 = Flush
[6:5] R/W Reserved. Program to zero.
[4:0] R RX FIFO data count. (0~16)
Address
0x5500000C IIS interface clock divider control register
Bit R/W
R/W Reserved. Program to zero.
[15] R/W Pre-scaler (Clock divider) active.
1 = Active (divide I2SAudioCLK with Pre-scaler division value)
0 = Inactive (bypass I2SAudioCLK) (Refer to Figure 23-2)
[14] R/W Reserved. Program to zero.
[13:8] R/W Pre-scaler (Clock divider) division value.
N: Division factor is N+1 (1~1/64)
[7:0] R/W Reserved. Program to zero.
S3C2416X RISC MICROPROCESSOR
Description
Description
Description
Description
Reset Value
0x0000_0000
Reset Value
0x0000_0000