Uart Fifo Control Register - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

3.3 UART FIFO CONTROL REGISTER

There are four UART FIFO control registers including UFCON0, UFCON1, UFCON2 and UFCON3 in the UART
block.
Register
UFCON0 0x50000008
UFCON1 0x50004008
UFCON2 0x50008008
UFCON3 0x5000C008
UFCONn
Tx FIFO Trigger [7:6]
Level
(note 2)
Rx FIFO Trigger [5:4]
Level
(note 2)
Reserved
Tx FIFO Reset
Rx FIFO Reset
FIFO Enable
(note 2)
NOTES:
1. At DMA mode, FIFO Enable should be Disabled.
2. Please refer the following recommendation for Interrupt / DMA mode.
Mode
Interrupt mode
DMA mode
Address R/W
R/W UART channel 0 FIFO control register
R/W UART channel 1 FIFO control register
R/W UART channel 2 FIFO control register
R/W UART channel 3 FIFO control register
Bit
Determine the trigger level of transmit FIFO.
00 = Empty
01 = 16-byte
10 = 32-byte
11 = 48-byte
Determine the trigger level of receive FIFO.
00 = 1-byte
01 = 8-byte
10 = 16-byte
11 = 32-byte
[3] −
[2] Auto-cleared after resetting FIFO
0 = Normal
1 = Tx FIFO reset
[1] Auto-cleared after resetting FIFO
0 = Normal
1 = Rx FIFO reset
[0]
0 = Disable
(note 1)
1 = Enable
FIFO enable
Enable (FIFO mode)
Disable (Non-FIFO
mode)
Description
Description
TX FIFO RX FIFO
Trigger level Trigger level
16~48byte 8~32byte
n/a n/a
UART
Reset Value
0x0
0x0
0x0
0x0
Initial State
00
00
0
0
0
0
RX time out
enable
enable
n/a
14-15