S3C2416X RISC MICROPROCESSOR
HSMMC CONTROLLER
Figure 20-14. Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with data transfer
Figure 20-15. Timing of Command Inhibit (DAT) for the case of response with busy
Figure 20-16. Timing of Command Inhibit (CMD) for the case of no response command
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