Samsung S3C2416 User Manual page 20

Figure
Number
1-1
1-2
1-3
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
3-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
6-1
6-2
6-3
6-4
6-5
6-6
6-7
S3C2416X RISC MICROPROCESSOR
List of Figures
S3C2416 Block Diagram ............................................................................................. 1-5
S3C2416 Pin Assignments (400-FBGA) Top view...................................................... 1-6
Memory Map ................................................................................................................ 1-32
System Controller Block Diagram................................................................................ 2-2
Power-On Reset Sequence......................................................................................... 2-4
Clock Generator Block Diagram .................................................................................. 2-6
Main Oscillator Circuit Examples................................................................................. 2-7
PLL(Phase-Locked Loop) Block Diagram ................................................................... 2-8
The Case that Changes Slow Clock by Setting PMS Value........................................ 2-8
The Clock Distribution Block Diagram ......................................................................... 2-9
MPLL Based Clock Domain......................................................................................... 2-9
EPLL Based Clock Domain ......................................................................................... 2-12
Power Mode State Diagram......................................................................................... 2-13
Entering STOP Mode and Exiting STOP Mode (wake-up).......................................... 2-17
Entering SLEEP Mode and Exiting SLEEP Mode (wake-up) ...................................... 2-18
Usage of PWROFF_SLP ............................................................................................. 2-34
The Configuration of MATRIX and Memory Sub-System of S3C2416 ....................... 3-1
SMC Block Diagram .................................................................................................... 5-3
SMC Core Block Diagram............................................................................................ 5-3
External Memory Two Output Enable Delay State Read ............................................ 5-4
Read Timing Diagram (DRnCS = 1, DRnOWE = 0).................................................... 5-4
Read Timing Diagram (DRnCS = 1, DRnOWE = 1).................................................... 5-5
External Burst ROM with WSTRD=2 and WSTBRD=1 Fixed Length Burst Read...... 5-6
External Synchronous Fixed Length Four Transfer Burst Read ................................. 5-7
External Memory Two Write Enable Delay State Write............................................... 5-8
Write Timing Diagram (DRnCS = 1, DRnOWE = 0) .................................................... 5-9
Write Timing Diagram (DRnCS = 1, DRnOWE = 1) .................................................... 5-9
Synchronous Two Wait State Write............................................................................. 5-10
Read, then two Writes (WSTRD=WSTWR=0), Two Turnaround Cycles (IDCY=2) ... 5-11
Memory Interface with 8-bit SRAM (2MB) ................................................................... 5-13
Memory Interface with 16-bit SRAM (4MB) ................................................................. 5-13
Mobile DRAM Controller Block Diagram ..................................................................... 6-2
Memory Interface with 16-bit SDRAM (4Mx16, 4banks) ............................................. 6-4
Memory Interface with 32-bit SDRAM (4Mx16 * 2ea, 4banks).................................... 6-4
Memory Interface with 16-bit Mobile DDR and DDR2................................................. 6-5
DRAM Timing Diagram................................................................................................ 6-6
CL (CAS Latency) Timing Diagram ............................................................................. 6-6
t Timing Diagram.................................................................................................. 6-7
ARFC
Title Page
Number
xix