Control Register 2 - Samsung S3C2416 User Manual

HSMMC CONTROLLER

5.27 CONTROL REGISTER 2

Register
CONTROL2_0 0X4AC00080
CONTROL2_1 0X4A800080
Name
CDINVRXD3
CDINVRXD3
SELCARDOUT
FLTCLKSEL
LVLDAT
ENFBCLKTX
ENFBCLKRX
SDCDSEL
20-64
Address R/W
R/W
R/W
Bit
[31]
Write Status Clear Async Mode Enable
This bit can make async-clear enable about Normal and Error
interrupt status bit. During the initialization procedure
command operation, this bit should be enabled.
0 = Disable
1 = Enable
[30]
Command Conflict Mask Enable
This bit can mask enable the Command Conflict Status (bit
[1:0] of the "ERROR INTERRUPT STATUS REGISTER")
0 = Mask Disable
1 = Mask Enable
[29]
Card Detect signal inversion for RX_DAT[3]
0 = Disable
1 = Enable
[28]
Card Removed Condition Selection
0 = Card Removed condition is "Not Card Insert" State (When
the transition from "Card Inserted" state to "Debouncing"
state)
1 = Card Removed state is "Card Out" State (When the
transition from "Debouncing state to "No Card" state)
[27:24] Filter Clock (iFLTCLK) Selection
Filter Clock period = 2^(FltClkSel + 5) x iSDCLK period
0000 = 25 x iSDCLK, 0001 = 26 x iSDCLK ... 1111 = 220 x
iSDCLK
[23:16] DAT line level
Bit[23]=DAT[7], BIT[22]=DAT[6], BIT[21]=DAT[5],
BIT[20]=DAT[4],
Bit[19]=DAT[3], BIT[18]=DAT[2], BIT[17]=DAT[1],
BIT[16]=DAT[0]
(Read Only)
[15]
Feedback Clock Enable for Tx Data/Command Clock
0 = Disable
1 = Enable
[14]
Feedback Clock Enable for Rx Data/Command Clock
0 = Disable
1 = Enable
[13]
SD Card Detect Signal Selection
Description
Control register 2 (Channel 0)
Control register 2 (Channel 1)
Description
S3C2416X RISC MICROPROCESSOR
Reset Value
Initial Value
0x0
0x0
0
0
0
0
0
Line state
0
0
0