Determination Of Transfer Type - Samsung S3C2416 User Manual

HSMMC CONTROLLER
Name Bit
ENBLKCNT [1]
ENDMA [0]
Table below shows the summary of how register settings determine types of data transfer.
Multi/Single Block Select
0
1
1
1
NOTE: For CE-ATA access, (Auto) CMD12 should be issued after Command Completion Signal Disable
20-24
Block Count Enable
This bit is used to enable the Block Count register, which is only relevant
for multiple block transfers. When this bit is 0, the Block Count register is
disabled, which is useful in executing an infinite transfer. (Refer to the
Table below "Determination of Transfer Type" )
1 = Enable
0 = Disable
DMA Enable
This bit enables DMA functionality. DMA can be enabled only if it is
supported as indicated in the DMA Support in the Capabilities register.
If DMA is not supported, this bit is meaningless and shall always read 0.
If this bit is set to 1, a DMA operation shall begin when the Host Driver
writes to the upper byte of Command register (00Fh).
1 = Enable
0 = Disable
Table 20-1. Determination of Transfer Type
Block Count Enable
Don't care
0
1
1
Description
Block Count
Don't care
Don't care
Not Zero
Zero
S3C2416X RISC MICROPROCESSOR
Initial Value
Function
Single Transfer
Infinite Transfer
Multiple Transfer
Stop Multiple Transfer
0
0