Samsung S3C2416 User Manual page 599

S3C2416X RISC MICROPROCESSOR
IISCON
FRXFULL
TXDMAPAUSE
RXDMAPAUSE
TXCHPAUSE
RXCHPAUSE
TXDMACTIVE
RXDMACTIVE
I2SACTIVE
NOTE: When playing is finished, Under-run interrupt will be occurring. (Since no more data are written into TXFIFO at the end
of playing.) User can stop transmission at this Under-run interrupt.
Bit R/W
[7] R
Rx FIFO full status indication.
0 = FIFO is not full (ready for receive data from channel)
1 = FIFO is full (not ready for receive data from channel)
[6] R/W
Tx DMA operation pause command. Note that when this bit is activated
at any time, the DMA request will be halted after current on-going DMA
transfer is completed.
0 = No pause DMA operation
1 = Pause DMA operation
[5] R/W
Rx DMA operation pause command. Note that when this bit is activated
at any time, the DMA request will be halted after current on-going DMA
transfer is completed.
0 = No pause DMA operation
1 = Pause DMA operation
[4] R/W
Tx channel operation pause command. Note that when this bit is
activated at any time, the channel operation will be halted after left-right
channel data transfer is completed.
0 = No pause operation
1 = Pause operation
[3] R/W
Rx channel operation pause command. Note that when this bit is
activated at any time, the channel operation will be halted after left-right
channel data transfer is completed.
0 = No pause operation
1 = Pause operation
[2] R/W
Tx DMA active (start DMA request). Note that when this bit is set from
high to low, the DMA operation will be forced to stop immediately.
0 = Inactive
1 = Active
[1] R/W
Rx DMA active (start DMA request). Note that when this bit is set from
high to low, the DMA operation will be forced to stop immediately.
0 = Inactive
1 = Active
[0] R/W
IIS interface active (start operation).
0 = Inactive
1 = Active
IIS MULTI AUDIO INTERFACE
Description
23-17