Arm & Bus Clock Divide Ratio - Samsung S3C2416 User Manual

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5.6 ARM & BUS CLOCK DIVIDE RATIO
The MSysClk is the base clock for S3C2416 system clock, such as ARMCLK, HCLK, PCLK, DDRCLK, etc.
The Table 2-5 shows the clock division ratios between ARMCLK, HLCK and PCLK. This ratio is determined by
ARMDIV, PREDIV, HCLKDIV and PCLKDIV bits of CLKDIV0 control register.
ARMCLK has to faster or equal with HCLK and synchronous. The Table 2-5 shows that DDRCLK, PCLK,
ARMCLK divide ratio with regard HCLK ratio.
The fraction in the cell is ratio to MSysClk and the value in the round bracket means maximum frequency value.
MSysClk
(800MHz) (133MHz)
1/1
1/2
1/3
1/4
1/6
1/8
1/12
1/16
2-10
Table 2-5. Clock Division Ratio of MPLL Region
HCLK DDRCLK
(266MHz)
1/1
1/1
1/1
1/2
1/3
1/4
1/6
1/8
PCLK, SSMC
(133MHz)
1/1 or 1/2
1/2 or 1/4
1/3 or 1/6
1/4 or 1/8
1/6 or 1/12
1/8 or 1/16
1/12 or 1/24
1/16 or 1/32
S3C2416X RISC MICROPROCESSOR
ARMCLK (400MHz)
1/1
1/1 or 1/2
1/1 or 1/3
1/1 or 1/2 or 1/4
1/1 or 1/2 or 1/3 or 1/6
1/1 or 1/2 or 1/4 or 1/8
1/1 or 1/2 or 1/3 or 1/4 or 1/6
1/1 or 1/2 or 1/4 or 1/8