Dma Fifo Counter Register (Dfcr) - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

8.19 DMA FIFO COUNTER REGISTER (DFCR)

This register has the byte number of data per DMA operation.
The max packet size is loaded in this register.
Register Address
DFCR 0x4980_0048
MFCR Bit
[31:12]
DFCR [11:0]
R/W
R/W DMA FIFO Counter Register
R/W
Reserved
−
R/W In case of OUT Endpoint, the size value of received packet
will be loaded in this register automatically when Rx DMA
Run is enabled.
In case of IN Endpoint, the MCU should set max packet
value.
Description
Description
USB2.0 DEVICE
Reset Value
0x0
Initial State
12'h0
16-27