Samsung S3C2416 User Manual page 9

Chapter 8
1 Overview ................................................................................................................................................... 8-1
2 DMA Request Sources ............................................................................................................................. 8-2
3 DMA Operation ......................................................................................................................................... 8-3
3.1 External DMA Dreq/Dack Protocol .................................................................................................. 8-4
3.2 Examples of Possible Cases........................................................................................................... 8-7
4 DMA Special Registers ............................................................................................................................. 8-8
4.1 DMA Initial Source Register (DISRC).............................................................................................. 8-8
4.2 DMA Initial Source Control Register (DISRCC) .............................................................................. 8-9
4.3 DMA Initial Destination Register (DIDST) ....................................................................................... 8-10
4.4 DMA Initial Destination Control Register (DIDSTC) ........................................................................ 8-11
4.5 DMA Control Register (DCON) ....................................................................................................... 8-12
4.6 DMA Status Register (DSTAT)........................................................................................................ 8-14
4.7 DMA Current Source Register (DCSRC) ........................................................................................ 8-15
4.8 Current Destination Register (DCDST) ........................................................................................... 8-15
4.9 DMA Mask Trigger Register (DMASKTRIG) ................................................................................... 8-16
4.10 DMA Requeset Selection Register (DMAREQSEL)...................................................................... 8-17
Chapter 9
1 Overview ................................................................................................................................................... 9-1
1.1 Interrupt Controller Operation.......................................................................................................... 9-3
1.2 Interrupt Sources ............................................................................................................................. 9-4
1.3 Interrupt Priority Generating Block .................................................................................................. 9-6
1.4 Interrupt Priority ............................................................................................................................... 9-7
2 Interrupt Controller Special Registers....................................................................................................... 9-8
2.1 Source Pending (SRCPND) Register.............................................................................................. 9-10
2.2 Interrupt Mode (INTMOD) Register ................................................................................................. 9-12
2.3 Interrupt Mask (INTMSK) Register .................................................................................................. 9-14
2.4 Interrupt Pending (INTPND) Register.............................................................................................. 9-16
2.5 Interrupt Offset (INTOFFSET) Register........................................................................................... 9-18
2.6 Sub Source Pending (SUBSRCPND) Register............................................................................... 9-20
2.7 Interrupt Sub Mask (INTSUBMSK) Register ................................................................................... 9-22
2.8 Priority Mode Register (priority_MODE).......................................................................................... 9-24
2.9 Priority Update Register (priority_UPDATE) ................................................................................... 9-29
S3C2416X RISC MICROPROCESSOR
Table of Contents
DMA Controller
Interrupt Controller
(Continued)
vii