Samsung S3C2416 User Manual page 508

HSMMC CONTROLLER
Name
CAPAMAXBLKLEN
CAPABASECLK
CAPATOUTUNIT
CAPATOUTCLK
20-62
Bit
[17:16] Max Block Length (HWInit)
This value indicates the maximum block size that the Host
Driver can read and write to the buffer in the Host Controller.
The buffer shall transfer this block size without wait cycles.
Three sizes can be defined as indicated below.
00 = 512-byte
01 = 1024-byte
10 = 2048-byte
11 = Reserved
[15:14] Reserved
[13:8] Base Clock Frequency For SD Clock (HWInit)
This value indicates the base (maximum) clock frequency for
the SD Clock. Unit values are 1MHz. If the real frequency is
16.5MHz, the lager value shall be set 01 0001b (17MHz)
because the Host Driver use this value to calculate the clock
divider value (Refer to the SDCLK Frequency Select in the
Clock Control register.) and it shall not exceed upper limit of
the SD Clock frequency. The supported clock range is 10MHz
to 63MHz. If these bits are all 0, the Host System has to get
information via another method.
Not 0 = 1MHz to 63MHz
000000b = Get information via another method
[7] Timeout Clock Unit (HWInit)
This bit shows the unit of base clock frequency used to detect
Data Timeout Error.
0 = kHz
1 = MHz
[6]
Reserved
[5:0] Timeout Clock Frequency (HWInit)
This bit shows the base clock frequency used to detect Data
Timeout Error. The Timeout Clock Unit defines the unit of
this field value.
Timeout Clock Unit =0 [kHz] unit: 1kHz to 63kHz
Timeout Clock Unit =1 [MHz] unit: 1MHz to 63MHz
Not 0 = 1kHz to 63kHz or 1MHz to 63MHz
00 0000b = Get information via another method
S3C2416X RISC MICROPROCESSOR
Description Initial Value
0
0
0
1
0
0