S3C2416X RISC MICROPROCESSOR
4
BUS PRIORITIES
1 OVERVIEW
The bus arbitration logic determines the priorities of bus masters. It supports a combination of rotation priority
mode and fixed priority mode.
1.1
BUS PRIORITY MAP
The S3C2416 holds 16 masters on the AHB_S(System Bus), 9 masters on the AHB_I(Image Bus) and 9masters
on the APB Bus. The following list shows the priorities among these bus masters after a reset.
Priority
AHB_S BUS MASTERS
0
1
2
3
4
5
6
7
8
9
10
11
UDEVICE20
12
13
ARM926EJ DBUS
14
ARM926EJ IBUS
15
Reserved
1. Fix Type: all priority can be changed according to register value
stored in The System Controller.
HS-MMC1
DMA0
2 Rotation Type: all masters' priority can be rotatable according to
DMA1
register value stored in The System Controller.
DMA2
(Except for Default Masters)
DMA3
DMA4
DMA5
Reserved
Reserved
UHOST
HS-MMC0
Default
Comment
BUS PRIORITIES
4-1