Burst 4 Transfer Size - Samsung S3C2416 User Manual

DMA CONTROLLER
3.1.4 Transfer Size
• There are two different transfer sizes; single and Burst 4.
• DMA holds the bus firmly during the transfer of these chunk of data, thus other bus masters can not get the
bus.

3.1.5 Burst 4 Transfer Size

4 sequential Reads and 4 sequential Writes are performed in the Burst 4 Transfer.
XSCLK
XnXDREQ
XnXDACK
Double
synch
8-6
Single Transfer size: One read and one write are performed.
3 cycles
Figure 8-3. Burst 4 Transfer size
NOTE
Read Read Read
S3C2416X RISC MICROPROCESSOR
Read Write Write Write Write