Pll (Phase-Locked-Loop); Change Pll Settings In Normal Operation - Samsung S3C2416 User Manual

SYSTEM CONTROLLER
5.3

PLL (PHASE-LOCKED-LOOP)

The PLL (Phase-Locked Loop) frequency synthesizer is constructed in CMOS on single monolithic structure. The
PLL provides frequency multiplication capabilities.
MPLL generates the clock sources for ARMCLK, HCLK, PCLK, DDRCLK and SSMCCLK and EPLL generates
clock sources for USBHOSTCLK, CAMCLK and so forth.
The following sections describe the operation of the PLL, that includes the phase difference detector, charge
pump, VCO (Voltage controlled oscillator), and loop filter.
Refer to MPLLCON and EPLLCON registers to change PLL output frequency.
Fin Pre-Divider
5.4

CHANGE PLL SETTINGS IN NORMAL OPERATION

During the operation of S3C2416 in NORMAL mode, if the user wants to change the frequency by writing the PMS
value, the PLL lock time is automatically inserted. During the lock time, the clock is not supplied to the internal
blocks in S3C2416. The timing diagram is as follow.
MPLL_clk
SYSCLK
Figure 2-6. The Case that Changes Slow Clock by Setting PMS Value
2-8
Charge
PFD
Figure 2-5. PLL(Phase-Locked Loop) Block Diagram
It changes to LOW value during
lock time automatically
Off-chip loop filter
VCO
Pump
Main
Divider
PMS setting
PLL Locktime
It changes to new PLL clock
after lock time automatically
S3C2416X RISC MICROPROCESSOR
Post
Fout
Scaler