Samsung S3C2416 User Manual page 442

HS_SPI CONTROLLER
Register
HS_SPI_STATUS(Ch0
)
HS_SPI_STATUS
TX_done
Trailing_count_done
RxFifoLvl
TxFifoLvl
RxOverrun
RxUnderrun
TxOverrun
TxUnderrun
RxFifoRdy
TxFifoRdy
19-10
Address R/W
0x52000014 R
Bit
Indication of transfer done in Shift register
0 = all case except blow case
[21]
1 = when tx fifo and shift register are empty
* Master mode only
[20] Indication that trailing count is zero
Data level in RX FIFO
[19:13]
0 ~ 7'h40 byte
Data level in TX FIFO
[12:6]
0 ~ 7'h40 byte
Rx Fifo overrun error
[5]
0 = No error
1 = Overrun error
Rx Fifo underrun error
[4]
0 = No error
1 = Underrun error
Tx Fifo overrun error
[3]
0 = No error
1 = Overrun error
Tx Fifo underrun error
0 = No error
[2]
1 = Underrun error
* If TX fifo empty, always occur at slave mode
0 = Data in FIFO less than trigger level
[1]
1 = Data in FIFO more than trigger level
0 = Data in FIFO more than trigger level
[0]
1 = Data in FIFO less than trigger level
Description
HS_SPI status register
Description
S3C2416X RISC MICROPROCESSOR
Reset Value
Initial State
0x0
1'b0
1'b0
7'b0
7'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0