Samsung S3C2416 User Manual page 70

16/32-bit risc
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PRODUCT OVERVIEW
Register Name
ESR
ECR
BRCR
BWCR
MPR
DCR
DTCR
DFCR
DTTCR1
DTTCR2
MICR
MBAR
MCAR
Watchdog Timer
WTCON
WTDAT
WTCNT
IIC
IICCON0
IICSTAT0
IICADD0
IICDS0
IICLC0
IIS Multi Audio Interface
IISCON
IISMOD
I2SFIC
I2SPSR
I2STXD
I2SRXD
I/O port
GPACON
GPADAT
GPBCON
GPBDAT
GPBUDP
GPBSEL
1-42
Address
Reset Value
0x4980_002C
0x0
0x4980_0030
0x0
0x4980_0034
0x0
0x4980_0038
0x0
0x4980_003C
0x0
0x4980_0040
0x0
0x4980_0044
0x0
0x4980_0048
0x0
0x4980_004C
0x0
0x4980_0050
0x0
0x4980_0084
0x0
0x4980_0088
0x0
0x4980_008C
0x0
0x53000000
0x0000_8021
0x53000004
0x0000_8000
0x53000008
0x0000_8000
0x54000000
0x54000004
0x54000008
0x5400000C
0x54000010
0x55000000
0xC600
0x55000004
0x0
0x55000008
0x0
0x5500000C
0x0
0x55000010
0x0
0x55000014
0x0
0x56000000
0xFFFFFF
0x56000004
0x0
0x56000010
0x0
0x56000014
0x0
0x56000018
0x00155555
0x5600001c
0x1
S3C2416X RISC MICROPROCESSOR
Acc.
Read/
Unit
Write
R/W
Endpoints Status Register
R/W
Endpoints Control Register
R
Byte Read Count Register
R/W
Byte Write Count Register
R/W
Max Packet Register
R/W
DMA Control Register
R/W
DMA Transfer Counter Register
R/W
DMA FIFO Counter Register
R/W
DMA Total Transfer Counter1 Register
R/W
DMA Total Transfer Counter2 Register
R/W
Master Interface Control Register
R/W
Memory Base Address Register
R
Memory Current Address Register
W
R/W
Watchdog timer mode
Watchdog timer data
Watchdog timer count
W
R/W
IIC0 control
IIC0 status
IIC0 address
IIC0 data shift
IIC0 multi-master line control
W
R/W
IIS control
IIS mode
I2S interface FIFO control register
I2S interface clock divider control register
W
I2S interface transmit data register
R
I2S interface receive data register
W
R/W
Port A control
W
R/W
Port A data
W
R/W
Port B control
W
R/W
Port B data
W
R/W
Pull-up/down control B
W
R/W
Selects the function of port B
Function

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