Samsung S3C2416 User Manual page 174

NAND FLASH CONTROLLER
NFCONT
EnbIllegalAccINT
EnbRnBINT
RnB_TransMode
MainECCLock
SpareECCLock
InitMECC
InitSECC
Reserved
Reg_nCE1
Reg_nCE0
MODE
7-16
Bit
[10] Illegal access interrupt control
0 = Disable interrupt
1 = Enable interrupt
Illegal access interrupt will occurs when CPU tries to
program or erase locking area (the area setting in NFSBLK
(0x4E000020) to NFEBLK (0x4E000024)).
[9] RnB status input signal transition interrupt control
0 = Disable RnB interrupt
1 = Enable RnB interrupt
[8] RnB transition detection configuration
0 = Detect rising edge
1 = Detect falling edge
[7] Lock Main area ECC generation
0 = Unlock Main area ECC
1 = Lock Main area ECC
Main area ECC status register is
NFMECC0/1(0x4E000034/38),
[6] Lock Spare area ECC generation.
0 = Unlock Spare ECC
1 = Lock Spare ECC
Spare area ECC status register is NFSECC(0x4E00003C),
[5] 1 = Initialize main area ECC decoder/encoder (write-only)
[4] 1 = Initialize spare area ECC decoder/encoder (write-only)
[3] Reserved
[2] NAND Flash Memory nRCS[1] signal control
0 = Force nRCS[1] to low(Enable chip select)
1 = Force nRCS[1] to High(Disable chip select)
Note: Even Reg_nCE1 and Reg_nCE0 are set to zero
simultaneously, only one of them is asserted.
[1] NAND Flash Memory nFCE signal control
0 = Force nFCE to low(Enable chip select)
1 = Force nFCE to High(Disable chip select)
Note: During boot time, it is controlled automatically.
This value is only valid while MODE bit is 1
[0] NAND Flash controller operating mode
0 = NAND Flash Controller Disable (Don't work)
1 = NAND Flash Controller Enable
S3C2416 RISC MICROPROCESSOR
Description Initial State
0
0
0
1
1
0
0
0
1
1
0