Samsung S3C2416 User Manual page 479

S3C2416X RISC MICROPROCESSOR
Name Bit
[7:3]
DATLINEACT [2]
CMDINHDAT [1]
Reserved
DAT Line Active (ROC)
This bit indicates whether one of the DAT line on SD Bus is in use.
(a) In the case of read transactions
This status indicates if a read transfer is executing on the SD Bus.
Changes in this value from 1 to 0 between data blocks generate a
Block Gap Event interrupt in the Normal Interrupt Status register.
This bit shall be set in either of the following cases:
(1) After the end bit of the read command.
(2) When writing a 1 to Continue Request in the Block Gap Control
register to restart a read transfer.
This bit shall be cleared in either of the following cases:
(1) When the end bit of the last data block is sent from the SD Bus
to the Host Controller.
(2) When beginning a wait read transfer at a stop at the block gap
initiated by a Stop At Block Gap Request.
The Host Controller shall wait at the next block gap by driving Read
Wait at the start of the interrupt cycle. If the Read Wait signal is
already driven (data buffer cannot receive data), the Host Controller
can wait for current block gap by continuing to drive the Read Wait
signal. It is necessary to support Read Wait in order to use the
suspend / resume function.
(b) In the case of write transactions
This status indicates that a write transfer is executing on the SD
Bus. Changes in this value from 1 to 0 generate a Transfer
Complete interrupt in the Normal Interrupt Status register.
This bit shall be set in either of the following cases:
(1) After the end bit of the write command.
(2) When writing to 1 to Continue Request in the Block Gap Control
register to continue a write transfer.
This bit shall be cleared in either of the following cases:
(1) When the SD card releases write busy of the last data block the
Host Controller shall also detect if output is not busy. If SD card
does not drive busy signal for 8 SD Clocks, the Host Controller shall
consider the card drive "Not Busy".
(2) When the SD card releases write busy prior to waiting for write
transfer as a result of a Stop At Block Gap Request.
1 = DAT Line Active
0 = DAT Line Inactive
Data Inhibit (DAT) (ROC)
This status bit is generated if either the DAT Line Active or the
Read Transfer Active is set to 1. If this bit is 0, it indicates the Host
Controller can issue the next SD Command. Commands with busy
signal belong to Command Inhibit (DAT) (ex. R1b, R5b type).
Description
HSMMC CONTROLLER
Initial Value
0
0
0
20-33