Samsung S3C2416 User Manual page 488

HSMMC CONTROLLER
Name Bit
STBLEXTCLK [3]
ENSDCLK [2]
STBLINTCLK [1]
ENINTCLK [0]
20-42
External Clock Stable
This bit is set to 1 when SD Clock output is stable after writing to SD
Clock Enable in this register to 1. The SD Host Driver shall wait to
issue command to start until this bit is set to 1. (ROC)
1 = Ready
0 = Not Ready
SD Clock Enable
The Host Controller shall stop SDCLK when writing this bit to 0.
SDCLK Frequency Select can be changed when this bit is 0. Then,
the Host Controller shall maintain the same clock frequency until
SDCLK is stopped (Stop at SDCLK=0). If the Card Inserted in the
Present State register is cleared, this bit shall be cleared. (RW)
1 = Enable
0 = Disable
Internal Clock Stable
This bit is set to 1 when SD Clock is stable after writing to Internal
Clock Enable in this register to 1. The SD Host Driver shall wait to
set SD Clock Enable until this bit is set to 1.
Note: This is useful when using PLL for a clock oscillator that requires
setup time. (ROC)
1 = Ready
0 = Not Ready
Internal Clock Enable
This bit is set to 0 when the Host Driver is not using the Host
Controller or the Host Controller awaits a wakeup interrupt. The Host
Controller should stop its internal clock to go very low power state.
Still, registers shall be able to be read and written. Clock starts to
oscillate when this bit is set to 1. When clock oscillation is stable, the
Host Controller shall set Internal Clock Stable in this register to 1.
This bit shall not affect card detection. (RW)
1 = Oscillate
0 = Stop
S3C2416X RISC MICROPROCESSOR
Description Initial Value
0
0
0