Transfer Mode Register - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

5.6 TRANSFER MODE REGISTER

This register is used to control the operation of data transfers. The Host Driver shall set this register before issuing
a command which transfers data (see Data Present Select in the Command register), or before issuing a
Resume command. The Host Driver shall save the value of this register when the data transfer is suspended (as
a result of a Suspend command) and restore it before issuing a Resume command. To prevent data loss, the
Host Controller shall implement write protection for this register during data transactions. Writes to this register
shall be ignored when the Command Inhibit (DAT) in the Present State register is 1.
Register Address
TRNMOD0 0X4AC0000C
TRNMOD1 0X4A80000C
Name Bit
[15:10] Reserved
CCSCON [9:8]
[7:6]
MUL1SIN0 [5]
RD1WT0 [4]
[3]
ENACMD12 [2]
R/W
R/W Transfer Mode Setting Register (Channel 0)
R/W Transfer Mode Setting Register (Channel 1)
Command Completion Signal Control
00 = No CCS Operation (Normal operation, Not CE-ATA mode)
01 = Read or Write data transfer CCS enable (Only CE-ATA mode)
10 = Without data transfer CCS enable (Only CE-ATA mode)
11 = Abort Completion Signal (ACS) generation (Only CE-ATA mode)
Reserved
Multi / Single Block Select
This bit enables multiple block DAT line data transfers. For any other
commands, this bit shall be set to 0. If this bit is 0, it is not necessary to
set the Block Count register. (Refer to the Table below "Determination
of Transfer Type" )
1 = Multiple Block
0 = Single Block
Data Transfer Direction Select
This bit defines the direction of DAT line data transfers. The bit is set to
1 by the Host Driver to transfer data from the SD card to the SD Host
Controller and it is set to 0 for all other commands.
1 = Read (Card to Host)
0 = Write (Host to Card)
Reserved
Auto CMD12 Enable
Multiple block transfers for memory require CMD12 to stop the
transaction.
When this bit is set to 1, the Host Controller shall issue CMD12
automatically when last block transfer is completed. The Host Driver
shall not set this bit to issue commands that do not require CMD12 to
stop data transfer.
1 = Enable
0 = Disable
Description
Description
HSMMC CONTROLLER
Reset Value
0x0
0x0
Initial Value
0
0
0
0
0
0
0
20-23