Samsung S3C2500B User Manual

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查询S3C2500B供应商

捷多邦，专业PCB打样工厂，24小时加急出货

21-S3C2500B-032003

USER'S MANUAL

S3C2500B

32-Bit RISC

Microprocessor

Revision 1

Table of Contents

Summary of Contents for Samsung S3C2500B

Page 1 查询S3C2500B供应商捷多邦，专业PCB打样工厂，24小时加急出货 21-S3C2500B-032003 USER'S MANUAL S3C2500B 32-Bit RISC Microprocessor Revision 1...
Page 2 S3C2500B 32-BIT RISC MICROPROCESSOR USER'S MANUAL Revision 1...
Page 3: Important Notice
Samsung products are not designed, intended, or use of the information contained herein. authorized for use as components in systems Samsung reserves the right to make changes in its intended for surgical implant into the body, for other products or product specifications with the intent to...
Page 4: Table Of Contents
2.12 Reset ...............................2-16 2.13 Introduction for ARM940T ........................2-17 2.14 ARM940T Block Diagram.........................2-18 2.15 About The ARM940T Programmer's Model ..................2-19 2.15.1 Data Abort Model........................2-20 2.15.2 Instruction Set Extension Spaces..................2-20 2.16 ARM940T CP15 Registers .......................2-21 2.16.1 CP15 Register Map Summary ....................2-21 S3C2500B RISC MICROCONTROLLER...
Page 5 3.9.2 Shifted Register Offset......................3-29 3.9.3 Bytes and Words ........................3-29 3.9.4 Use of R15..........................3-31 3.9.5 Restriction on the Use of Base Register ................. 3-31 3.9.6 Data Aborts..........................3-31 3.9.7 Instruction Cycle Times......................3-31 3.9.8 Assembler Syntax........................3-32 S3C2500B RISC MICROCONTROLLER...
Page 6 3.14.4 Assembler Syntax.........................3-52 3.15 Coprocessor Data Transfers (LDC, STC) ..................3-53 3.15.1 The Coprocessor Fields ......................3-53 3.15.2 Addressing Modes ........................3-54 3.15.3 Address Alignment........................3-54 3.15.4 Use of R15 ...........................3-54 3.15.5 Data Aborts...........................3-54 3.15.6 Instruction Cycle Times ......................3-54 3.15.7 Assembler Syntax.........................3-55 S3C2500B RISC MICROCONTROLLER...
Page 7 3.25.2 Instruction Cycle Times......................3-76 3.26 Format 7: Load/Store With Register Offset..................3-77 3.26.1 Operation..........................3-77 3.26.2 Instruction Cycle Times......................3-78 3.27 Format 8: Load/Store Sign-Extended Byte/Half-Word ..............3-79 3.27.1 Operation..........................3-79 3.27.2 Instruction Cycle Times......................3-80 S3C2500B RISC MICROCONTROLLER...
Page 8 3.38 Format 19: Long Branch With Link....................3-95 3.38.1 Operation..........................3-95 3.38.2 Instruction Cycle Times ......................3-96 3.39 Instruction Set Examples .........................3-97 3.39.1 Multiplication by a Constant Using Shifts and Adds...............3-97 3.39.2 General Purpose Signed Divide....................3-98 3.39.3 Division by a Constant ......................3-100 S3C2500B RISC MICROCONTROLLER...
Page 9 5.7.4 SDRAM Commands....................... 5-44 5.7.5 External Data Bus Width......................5-45 5.7.6 Merging Write Buffer ......................5-45 5.7.7 Self Refresh........................... 5-45 5.7.8 Basic Operation ........................5-46 5.7.9 SDRAM Special Registers ..................... 5-47 5.7.10 SDRAM Controller Timing....................5-54 viii viii S3C2500B RISC MICROCONTROLLER...
Page 10 7.4.1 BDMA Relative Special Register ....................7-15 7.4.2 MAC Relative Special Register....................7-24 7.5 Ethernet Operations...........................7-37 7.5.1 MAC Frame Format........................7-37 7.5.2 The MII Station Manager ......................7-45 7.5.3 Full-Duplex Pause Operations ....................7-46 7.5.4 Error Signalling........................7-48 7.5.5 Timing Parameters for MII Transactions .................7-50 S3C2500B RISC MICROCONTROLLER...
Page 11 8.7.16 Transparent Control Register ....................8-52 8.7.17 Tx Buffer Descriptor Count Register..................8-53 8.7.18 Rx Buffer Descriptor Count Register ..................8-53 8.7.19 Tx Buffer Descriptor Maximum Count Register ..............8-54 8.7.20 Rx Buffer Descriptor Maximum Count Register..............8-54 S3C2500B RISC MICROCONTROLLER...
Page 12 9.5.8 IOM2 C/I1 Channel Receive Data Register................9-21 9.5.9 IOM2 Monitor Channel Transmit Data Register...............9-22 9.5.10 IOM2 Monitor Channel Receive Data Register..............9-22 9.5.11 TSA A Control Register......................9-23 9.5.12 TSA B Control Register......................9-24 9.5.13 TSA C Control Register ......................9-25 9.5.14 IOM2STRB (Strobe Register) ....................9-26 S3C2500B RISC MICROCONTROLLER...
Page 13 10.5.13 USB Write Count for Endpoint 1 Register................10-47 10.5.14 USB Write Count for Endpoint 2 Register................10-49 10.5.15 USB Write Count for Endpoint 3 Register................10-51 10.5.16 USB Write Count for Endpoint 4 Register................10-53 10.5.17 USB Endpoint 0/1/2/3/4 FIFO Register................10-55 S3C2500B RISC MICROCONTROLLER...
Page 14 12.5.3 Data Transfer Modes ......................12-18 12.6 GDMA Transfer Timing Data......................12-19 12.6.1 Single and One Data Burst Mode..................12-20 12.6.2 Single and Four Data Burst Mode ..................12-21 12.6.3 Block and One Data Burst Mode...................12-22 12.6.4 Block and Four Data Burst ....................12-23 S3C2500B RISC MICROCONTROLLER xiii...
Page 15 15.3.3 I/O Port Control Register for GDMA ..................15-8 15.3.4 I/O Port Control Register for External Interrupt..............15-9 15.3.5 I/O Port External Interrupt Clear Register................15-11 15.3.6 I/O Port Data Register......................15-12 15.3.7 I/O Port Drive Control Register .................... 15-12 S3C2500B RISC MICROCONTROLLER...
Page 16 17.6.5 Watchdog Timer Register .....................17-9 Chapter 18Electrical Data 18.1 Overview ............................18-1 18.2 Absolute Maximum Ratings ......................18-1 18.3 Recommended Operating Conditions....................18-1 18.4 DC Electrical Specifications ......................18-2 18.5 Max Power Consumption .........................18-4 18.6 AC Electrical Characteristics ......................18-5 Chapter 19Mechanical Data 19.1 Overview ............................19-1 S3C2500B RISC MICROCONTROLLER...
Page 18: List Of Figures
Title Page Number Number S3C2500B Block Diagram ..................1-5 S3C2500B Pin Assignment Diagram ..............1-6 Big-Endian Addresses of Bytes within Words............2-2 Little-Endian Addresses of Bytes Words ..............2-2 Register Organization in ARM State ...............2-5 Register Organization in THUMB State ..............2-6 Mapping of THUMB State Registers onto ARM State Registers......2-7 Program Status Register Format ................2-8...
Page 19 External Address Bus Diagram ................4-4 Priority Groups of S3C2500B................. 4-5 AHB Programmable Priority Registers ..............4-6 Shows the Clock Generation Logic of the S3C2500B..........4-14 Divided System Clock Timing Diagram..............4-19 Memory Bank Address map................... 5-4 Memory Controller Bus Signals................5-6 8-bit ROM, SRAM and Flash Basic Connection .............
Page 20 CSMA/CD Receive Operation ................7-44 7-12 MAC Control Frame Format ...................7-46 7-13 Timing Relationship of Transmission Signals at MII..........7-50 7-14 Timing Relationship of Reception Signals at MII.............7-50 7-15 MDIO Sourced by PHY...................7-50 7-16 MDIO Sourced by STA ...................7-50 S3C2500B RISC MICROCONTROLLER...
Page 21 IOM2 Control Register ................... 9-13 IOM2 Status Register .................... 9-15 IOM2 Interrupt Enable Register ................9-17 9-10 IOM2 TIC Bus Address Register ................9-18 9-11 IOM2 IC Channel Transmit Data Register.............. 9-19 9-12 IOM2 IC Channel Receive Data Register............... 9-19 S3C2500B RISC MICROCONTROLLER...
Page 22 10-13 USBEP1CSR Register....................10-29 10-14 USBEP2CSR Register....................10-34 10-15 USBEP3CSR Register....................10-39 10-16 USBEP4CSR Register....................10-44 10-17 USBWCEP0 Register.....................10-46 10-18 USBWCEP1 Register.....................10-48 10-19 USBWCEP2 Register.....................10-50 10-20 USBWCEP3 Register.....................10-52 10-21 USBWCEP4 Register.....................10-54 10-22 USBEP0/1/2/3/4 FIFO Registers ................10-56 11-1 DES/3DES Block Diagram ..................11-2 S3C2500B RISC MICROCONTROLLER...
Page 23 High-Speed UART Receive Buffer Register............14-17 14-7 High-Speed UART Baud Rate Divisor Register............14-18 14-8 High-Speed UART Baud Rate Generator (BRG)............ 14-19 14-9 High-Speed UART Control Character 1 Register............ 14-20 14-10 High-Speed UART Control Character 2 Register............ 14-21 xxii xxii S3C2500B RISC MICROCONTROLLER...
Page 24 Timer Output Signal Timing..................17-2 17-2 32-Bit Timer Block Diagram ...................17-3 17-3 Timer Mode Register....................17-5 17-4 Timer Data Registers....................17-6 17-5 Timer Counter Registers..................17-7 17-6 Timer Interrupt Clear Register ................17-8 17-7 Watchdog Timer Register..................17-9 19-1 272-BGA-2727-AN Package Dimensions..............19-2 S3C2500B RISC MICROCONTROLLER xxiii...
Page 26: List Of Tables
List of Tables Table Title Page Number Number S3C2500B Signal Descriptions ................1-13 S3C2500B Pad Type and Feature ................1-31 S3C2500B System Configuration ................1-32 S3C2500B Memory Controller ................1-32 S3C2500B SDRAM Controller ................1-32 S3C2500B IIC Controller ..................1-33 S3C2500B Ethernet Controller 0................1-33 S3C2500B Ethernet Controller 1................1-34 S3C2500B HDLC Controller 0 ................1-35...
Page 27 The Base Address of Remapped Memory.............. 4-3 AHB Bus Priorities for Arbitration................4-4 Clock Frequencies for CLKMOD Pins, CPU_FREQ Pins, and BUS_FREQ Pins ..4-9 P, M, S values of the S3C2500B PLL ..............4-13 System Configuration Registers................4-15 xxvi...
Page 28 SDRAM Write Buffer Time-out Register ..............5-53 Control Status Register...................6-9 IICCON Register Description ..................6-9 IICBUF Register .....................6-11 IICBUF Register Description...................6-11 IICPS Register .......................6-11 IICPS Register Description ..................6-11 IICCNT Register .....................6-12 IICCNT Register Description...................6-12 IICPND Register.....................6-12 6-10 IICPND Register Description ..................6-12 S3C2500B RISC MICROCONTROLLER xxvii...
Page 29 MAC Transmit Status Register Description ............7-28 7-36 MACRXCON Register.................... 7-29 7-37 MAC Receive Control Register Description............7-29 7-38 MACRXSTAT Register ..................7-30 7-39 MAC Receive Status Register Description ............. 7-30 7-40 STADATA Register....................7-31 xxviii xxviii S3C2500B RISC MICROCONTROLLER...
Page 30 DMA Rx Buffer Size Register .................8-51 8-23 Synchronization Register..................8-51 8-24 Transparent Control Register..................8-52 8-25 HTXBDCNTA, HTXBDCNTB, and HTXBDCNTC Register ........8-53 8-26 HRXBDCNTA, HRXBDCNTB, and HRXBDCNTC Register ........8-53 8-27 HTXBDMAXCNTA, HTXBDMAXCNTB, and HTXBDMAXCNTC Register ....8-54 8-28 HRXBDMAXCNTA, HRXBDMAXCNTB, and HRXBDMAXCNTC Register ....8-54 S3C2500B RISC MICROCONTROLLER xxix...
Page 31 USBDISCONN Register..................10-20 10-14 USBDISCONN Register Description ..............10-20 10-15 USBEP0CSR Register................... 10-22 10-16 USBEP0CSR Register Description ................ 10-22 10-17 USBEP1CSR Register................... 10-25 10-18 USBEP1CSR Register Description ................ 10-25 10-19 USBEP2CSR Register................... 10-30 10-20 USBEP2CSR Register Description ................ 10-30 S3C2500B RISC MICROCONTROLLER...
Page 32 GDMA Special Registers Overview ................12-3 12-2 GDMA Programmable Priority Registers ..............12-4 12-3 DCON0/1/2/3/4/5 Registers ..................12-9 12-4 GDMA Control Register Description ...............12-9 12-5 DSAR0/1/2/3/4/5 and DDAR0/1/2/3/4/5 Registers...........12-12 12-6 DTCR0/1/2/3/4/5 Registers..................12-13 12-7 DRER0/1/2/3/4/5 Registers..................12-14 12-8 DIPR0/1/2/3 Registers ....................12-15 S3C2500B RISC MICROCONTROLLER xxxi...
Page 33 HUBRD0 and HUBRD0 Registers................14-18 14-14 Typical Baud Rates Examples of High-Speed UART ..........14-19 14-15 HUCHAR1 Registers ..................... 14-20 14-16 HUCHAR2 Registers ..................... 14-21 14-17 HUABB Registers ....................14-22 14-18 HUABT Registers ....................14-23 xxxii xxxii S3C2500B RISC MICROCONTROLLER...
Page 34 17-6 Watchdog Timer Timeout Value ................17-10 18-1 Absolute Maximum Ratings..................18-1 18-2 Recommended Operating Conditions ..............18-1 18-3 D.C Electric Characteristics ..................18-2 18-4 Operating Frequency....................18-4 18-5 Clock AC timing specification .................18-4 18-6 AC Electrical Characteristics for S3C2500B ............18-5 S3C2500B RISC MICROCONTROLLER xxxiii...
Page 35: Product Overview
This highly integrated microcontroller enables customers to save system costs and increase performance over other 32-bit microcontroller. The S3C2500B is built based on an outstanding CPU core: The ARM940T cached processor is a member of the ARM9 Thumb family of high-performance 32-bit system-on-a-chip processor solutions.
Page 36: Features
PRODUCT OVERVIEW S3C2500B 1.2 FEATURES ARM940T Core processor On-chip CAM (21 addresses) • • Fully 16/32-bit RISC architecture. Full-duplex mode for doubled bandwidth • • Harvard cache architecture with separate 4KB Pause operation hardware support for full- Instruction and Data cache duplex flow control •...
Page 37 S3C2500B PRODUCT OVERVIEW 1.2 FEATURES (Continue) IOM2 Controller General DMA Channels • • IOM2 terminal mode support Six GDMA channels • • Inter-device communication via IC channel Memory to memory data transfer • • TIC bus access control Memory to peripheral data transfer (high-speed UART, DES, and USB controller) •...
Page 38 PRODUCT OVERVIEW S3C2500B 1.2 FEATURES (Continue) PLL3 for PHY C Controller • • The input frequency is 10MHz Master mode operation only • • Provide 20MHz or 25MHz output to external Baud rate generator for serial clock PHY chip Four PLLs for System, Core, USB and PHY...
Page 39: Block Diagram
Sys. Bus 3DES Arbiter 2-bank SDRAM USB 1.1 Memory Function Controller GDMA 8-bank Flash/ROM/ SRAM/Ext Timers REQ/ACK External Clock Gen. Bus Master & Reset Drv. with 4 PLLs 20 MHz or 10 MHz 25 MHz OSC. Figure 1-1. S3C2500B Block Diagram...
Page 40: Package Diagram
PRODUCT OVERVIEW S3C2500B 1.4 PACKAGE DIAGRAM TOP View A1 ball pad corner Figure 1-2. S3C2500B Pin Assignment Diagram...
Page 41: Pin Assignment
S3C2500B PRODUCT OVERVIEW 1.5 PIN ASSIGNMENT Pin # Pin Name Direction Pin # Pin Name Direction ADDR17 PHY_FREQ ADDR15 HnRTS2/GPIO59 ADDR11 HTXD2/GPIO56 ADDR8 HnCTS1/GPIO52 ADDR5 HRXD1/GPIO49 ADDR1 HTXC0/FSC/GPIO47 XDATA27 HnCTS0/GPIO44 XDATA26 HTXD0/DU XDATA23 ADDR20 XDATA21 ADDR19 TXD0_0/TXD_10M ADDR16 MDC_0 ADDR12...
Page 42 PRODUCT OVERVIEW S3C2500B 1.5 PIN ASSIGNMENT (Continue) Pin # Pin Name Direction Pin # Pin Name Direction TXD0_1/LOOP10M XDATA13 MDIO_0 XDATA10 COL_0 RXD0_0/RXD_10M RX_CLK_0 HnCTS2/GPIO60 TX_ERR_0/PCOMP_10M VDD1.8 VDD1.8 HnDCD1/GPIO53 VDD3.3 XDATA12 HnRTS0/STRB/GPIO43 XDATA9 ADDR23/ALE XDATA7 VDD1.8 RXD0_2 ADDR13 RXD0_1 VDD3.3...
Page 43 S3C2500B PRODUCT OVERVIEW 1.5 PIN ASSIGNMENT (Continued) Pin # Pin Name Direction Pin # Pin Name Direction VDD1.8_A VDD1.8_A USB_CLKSEL VDD1.8 USB_D- CPU_FILTER USB_D+ XDATA1 VDD3.3 XDATA0 nWBE1/nBE1/DQM1 nSDCAS nWBE0/nBE0/DQM0 nSDRAS nWBE2/nBE2/DQM2 VDD1.8_A VDD1.8 VDD1.8 BUS_FILTER PHY_FILTER VDD1.8 nSDCS1 nRCS5...
Page 44 PRODUCT OVERVIEW S3C2500B 1.5 PIN ASSIGNMENT (Continued) Pin # Pin Name Direction Pin # Pin Name Direction VDD1.8_A TX_ERR_1/PCOMP_10M VDD1.8 RXD1_0/RXD_10M USB_FILTER BUS_FREQ2 CPU_FREQ2 XBMREQ nRCS2 XBMACK nRCS3 TX_EN_1 nRCS4 CRS_1 RXD1_1 MDC_1 COL_1 USB_XCLK TXD1_1/LOOP_10M VDD3.3 B0SIZE1 HURXD1/GPIO35 nRCS0...
Page 45 S3C2500B PRODUCT OVERVIEW 1.5 PIN ASSIGNMENT (Continued) Pin # Pin Name Direction Pin # Pin Name Direction RX_CLK_1 RXD1_3 RXD1_2 RX_ERR_1 RX_DV_1/LINK10M CUTXD HUTXD0/ GPIO29 HURXD0/GPIO28 UCLK HUnRTS0/GPIO32 HUnDCD0/GPIO34 XCLK HUnDTR1/GPIO37 HUnDSR1/GPIO38 HUnCTS1/GPIO40 HUnDCD1/GPIO41 GPIO1 GPIO2 GPIO5 GPIO4 xINT1/GPIO9 xINT0/GPIO8...
Page 46 PRODUCT OVERVIEW S3C2500B 1.5 PIN ASSIGNMENT (Continued) Pin # Pin Name Direction Pin # Pin Name Direction CURXD GPIO7 CLKSEL xINT3/GPIO11 HUnDTR0/GPIO30 xGDMA_Req1/GPIO15 HUnDSR0/GPIO31 xGDMA_Ack0/GPIO18 HUnCTS0/GPIO33 xGDMA_Ack2/GPIO20 HUTXD1/GPIO36 TIMER1/GPIO23 HUnRTS1/GPIO39 HCLKO GPIO3 GPIO6 nTRST 1-12...
Page 47: Signal Description
Pin Name Type Pad Type Description System XCLK Phic S3C2500B PLL Clock Source. If CLKSEL is Config Low, PLL output clock is used as the system (20) clock. If CLKSEL is high, XCLK is used as the system clock. HCLKO phbst24 System clock output.
Page 48 System Bus Clock Frequency Selection. nRESET phis Not Reset. NRESET is the global reset input for the S3C2500B and nRESET must be held to "low" for at least 64 clock cycles for digital filtering. TMODE phicd Test Mode. The TMODE pin setting is...
Page 49 ADDR[10]/AP. XDATA[31:0] phbsut20 External bi-directional 32bit data bus. The S3C2500B supports 8 bit, 16bit, 32bit bus with ROM/SRAM/Flash/Ext IO bank, but supports 16 bit or 32 bit bus with SDRAM bank. nSDCS[1:0] phot20 Not chip select strobe for SDRAM.
Page 50 Not ROM/SRAM/Flash/ External I/O Chip select. The S3C2500B supports upt to 8 banks of ROM/SRAM/Flash/ External I/O. By controlling the nRCS signals, you can map CPU address into the physical memory banks. B0SIZE[1:0] phic Bank 0 Data Bus Access Size.
Page 51 SDRAM refresh operation. The XBMREQ is deactivated when the external bus master releases the external bus. When this occurs, the S3C2500B can get the control of the bus and the XBMACK goes “low”. XBMACK phob8 External bus Acknowledge.
Page 52 PRODUCT OVERVIEW S3C2500B Table 1-1. S3C2500B Signal Descriptions (Continue) Group Pin Name Type Pad Type Description Ethernet MDC_0 phob12 Management Data Clock. Controller0 The signal level at the MDC pin is used as a (18) timing reference for data transfers that are controlled by the MDIO signal.
Page 53 S3C2500B PRODUCT OVERVIEW Table 1-1. S3C2500B Signal Descriptions (Continue) Group Pin Name Type Pad Type Description Ethernet TX_EN_0 phob4 Transmit Enable/Transmit Enable for 10M. Controller0 TX_EN provides precise framing for the data (18) carried on TXD[3:0]. This pin is active during...
Page 54 PRODUCT OVERVIEW S3C2500B Table 1-1. S3C2500B Signal Descriptions (Continue) Group Pin Name Type Pad Type Description Ethernet CRS_0 phis Carrier Sense/Carrier Sense for 10M. Controller0 CRS is asserted asynchronously with (18) minimum delay from the detection of a non- idle medium in MII mode. CRS_10M is asserted when a 10-Mbit/s PHY has data to transfer.
Page 55 S3C2500B PRODUCT OVERVIEW Table 1-1. S3C2500B Signal Descriptions (Continue) Group Pin Name Type Pad Type Description Ethernet RX_ERR_0 phisd Receive Error. Controller0 PHY asserts RX_ERR synchronously (18) whenever it detects a physical medium error (e.g., a coding violation). PHY asserts RX_ERR only when it asserts RX_DV.
Page 56 PRODUCT OVERVIEW S3C2500B Table 1-1. S3C2500B Signal Descriptions (Continue) Group Pin Name Type Pad Type Description Ethernet TXD1[3:0]/ phob12 Transmit Data/Transmit Data for 10M. Controller1 TXD_10M/ Transmit data is aligned on nibble boundaries. (18) LOOP_10M TXD[0] corresponds to the first bit to be...
Page 57 S3C2500B PRODUCT OVERVIEW Table 1-1. S3C2500B Signal Descriptions (Continue) Group Pin Name Type Pad Type Description Ethernet TX_ERR_1/ phob4 Transmit Error/Packet Compression Enable Controller1 PCOMP_10M for 10M. (18) TX_ERR is driven synchronously to TX_CLK and sampled continuously by the Physical Layer Entity, PHY.
Page 58 PRODUCT OVERVIEW S3C2500B Table 1-1. S3C2500B Signal Descriptions (Continue) Group Pin Name Type Pad Type Description Ethernet RX_CLK_1 phis Receive Clock/Receive Clock for 10M. Controller1 RX_CLK is a continuous clock signal. Its (18) frequency is 25 MHz for 100-Mbit/s operation, and 2.5 MHz for 10-Mbit/s.
Page 59 S3C2500B PRODUCT OVERVIEW Table 1-1. S3C2500B Signal Descriptions (Continue) Group Pin Name Type Pad Type Description HDLC0 HTXD0/DU phbsud4 IOM2 Data Upstream. Open Drain Output and schmit trigger input. HDLC Ch-0 Transmit Data. The serial data output from the transmitter is encoded in NRZ/NRZI/ FM/Manchester data format.
Page 60 Pad Type Description HDLC0 HnCTS0/ phbst8 HDLC Ch-0 Clear To Send. GPIO44 The S3C2500B stores each transition of nCTS to ensure that its occurrence will be acknowledged by the system. General I/O Port. HnDCD0/ phbst8 HDLC Ch-0 Data Carrier Detected.
Page 61 S3C2500B PRODUCT OVERVIEW Table 1-1. S3C2500B Signal Descriptions (Continue) Group Pin Name Type Pad Type Description HDLC1 HTXD1/GPIO48 phbst16 HDLC Ch-1 Transmit Data. See the HTXD0 description General I/O Port. HRXD1/GPIO49 phbst8 HDLC Ch-1 Receive Data. See the HRXD0 description General I/O Port.
Page 62 PRODUCT OVERVIEW S3C2500B Table 1-1. S3C2500B Signal Descriptions (Continue) Group Pin Name Type Pad Type Description HDLC2 HnDCD2/ phbst8 HDLC Ch-2 Data Carrier Detected. GPIO61 See the HnDCD0 description General I/O Port HRXC2/ phbst8 HDLC Ch-2 Receiver Clock. GPIO62 See the HRXC0 description...
Page 63 S3C2500B PRODUCT OVERVIEW Table 1-1. S3C2500B Signal Descriptions (Continue) Group Pin Name Type Pad Type Description HUART0 HUnDSR0/ phbst8 Not HUART0 Data Set Ready. GPIO31 This input signals in the HUART0 that the peripheral (or host) is ready to transmit or...
Page 64 PRODUCT OVERVIEW S3C2500B Table 1-1. S3C2500B Signal Descriptions (Continue) Group Pin Name Type Pad Type Description HUART1 HUnDTR1/ phbst8 Not HUART1 Data Terminal Ready.. GPIO37 See HUnDTR0description General I/O Port HUnDSR1/ phbst8 Not HUART1 Data Set Ready. GPIO38 See HUnDSR0 description...
Page 65: Pad Type
– Open drain buffer Pbusbfs USB Buffer – NOTE: For the detail information about the pad type, “Input/Output Cells of the STD130/MDL130 0.18µm 3.3V Standard Cell Library Data Book” which is produced by Samsung Electronics Co., Ltd, ASIC Team. 1-31...
Page 66: Special Registers
PRODUCT OVERVIEW S3C2500B 1.8 SPECIAL REGISTERS Table 1-3. S3C2500B System Configuration Registers Address Description Reset Value SYSCFG 0xF0000000 System configuration register – PDCODE 0xF0000004 Product code and revision number register 0x25000000 CLKCON 0xF0000008 System clock control register 0x00000000 PCLKDIS 0xF000000C...
Page 67 0xF00F0008 Prescaler register 0x00000000 IICCNT 0xF00F000C Prescaler counter register 0x00000000 IICPND 0xF00F0010 Interrupt pending register 0x00000000 Table 1-7. S3C2500B Ethernet Controller 0 Registers Address Description Reset Value BDMATXCONA 0xF00A0000 Buffered DMA transmit control register 0x00000000 BDMARXCONA 0xF00A0004 Buffered DMA receive control register...
Page 68 PRODUCT OVERVIEW S3C2500B Table 1-8. S3C2500B Ethernet Controller 1 Registers Address Description Reset Value BDMATXCONB 0xF00C0000 Buffered DMA transmit control register 0x00000000 BDMARXCONB 0xF00C0004 Buffered DMA receive control register 0x00000000 BDMATXDPTRB 0xF00C0008 Transmit buffer descriptor start address 0x00000000 BDMARXDPTRB 0xF00C000C...
Page 69 S3C2500B PRODUCT OVERVIEW Table 1-9. S3C2500B HDLC Controller 0 Registers Address Description Reset Value HMODE HDLC mode register 0×F0100000 0×00000000 HCON 0×F0100004 HDLC control register 0×00000000 HSTAT 0×F0100008 HDLC status register 0×00000000 HINTEN 0×F010000C HDLC interrupt enable register 0×00000000 HTxFIFOC HTxFIFO frame continue register –...
Page 70 PRODUCT OVERVIEW S3C2500B Table 1-10. S3C2500B HDLC Controller 1 Registers Address Description Reset Value HMODE HDLC mode register 0×F0110000 0×00000000 HCON 0×F0110004 HDLC control register 0×00000000 HSTAT 0×F011F0008 HDLC status register 0×00000000 HINTEN 0×F011F000C HDLC interrupt enable register 0×00000000 HTxFIFOC HTxFIFO frame continue register –...
Page 71 S3C2500B PRODUCT OVERVIEW Table 1-11. S3C2500B HDLC Controller 2 Registers Address Description Reset Value HMODE HDLC mode register 0×F0120000 0×00000000 HCON 0×F0120004 HDLC control register 0×00000000 HSTAT 0×F0120008 HDLC status register 0×00000000 HINTEN 0×F012000C HDLC interrupt enable register 0×00000000 HTxFIFOC HTxFIFO frame continue register –...
Page 72 PRODUCT OVERVIEW S3C2500B Table 1-12. S3C2500B IOM2 Controller Register Address Description Reset Value IOM2CON 0xF0130000 Control Register 0x00000000 IOM2STAT 0xF0130004 Status Register 0x00000080 IOM2INTEN 0xF0130008 Interrupt Enable Register 0x00000000 IOM2TBA 0xF013000C TIC Bus Address 0x00000007 IOM2ICTD 0xF0130010 IC Channel Tx Buffer...
Page 73 S3C2500B PRODUCT OVERVIEW Table 1-13. S3C2500B USB Controller Register Address Description Reset Value USBFA 0xF00E0000 USB function address register 0x00000000 USBPM 0xF00E0004 USB power management register 0x00000000 USBINTR 0xF00E0008 USB interrupt register 0x00000000 USBINTRE 0xF00E000C USB interrupt enable register 0x00000000...
Page 74 PRODUCT OVERVIEW S3C2500B Table 1-14. S3C2500B DES Controller Registers Address Description Reset Value DESCON 0xF0090000 DES/3DES control register 0×00000000 DESSTA 0xF0090004 DES/3DES status register 0x00000231 DESINT 0xF0090008 DES/3DES interrupt enable register 0x00000000 DESRUN 0xF009000C DES/3DES run enable register 0x00000000 DESKEY1L...
Page 75 S3C2500B PRODUCT OVERVIEW Table 1-15. S3C2500B GDMA Controller Registers Address Description Reset Value DPRIC 0xF0051000 GDMA priority configuration register 0x00000000 DPRIF 0xF0052000 GDMA programmable priority register for fixed 0x00543210 DPRIR 0xF0053000 GDMA programmable priority register for round- 0x00000000 robin DCON0...
Page 76 Console UART baud rate divisor register 0x0000 CUCHAR1 0xF0060018 Console UART control character register 1 0x00000000 CUCHAR2 0xF006001C Console UART control character register 2 0x00000000 Table 1-17. S3C2500B High-speed UART Controller 0 Register Address Description Reset Value HUCON 0xF0070000 High-Speed UART control register 0x00000000 HUSTAT...
Page 77 S3C2500B PRODUCT OVERVIEW Table 1-18. S3C2500B High speed UART Controller 1 Register Address Description Reset Value HUCON 0xF0080000 High-Speed UART control register 0x00000000 HUSTAT 0xF0080004 High-Speed UART status register – HUINT 0xF0080008 High-Speed UART interrupt enable register 0x00000000 HUTXBUF 0xF008000C High-Speed UART transmit data register –...
Page 78 PRODUCT OVERVIEW S3C2500B Table 1-20. S3C2500B Interrupt Controller Register Address Description Reset Value INTMOD 0xF0140000 Internal interrupt mode register 0x00000000 EXTMOD 0xF0140004 External interrupt mode register 0x00000000 INTMASK 0xF0140008 Internal Interrupt mask register 0xFFFFFFFF EXTMASK 0xF014000C External Interrupt mask register...
Page 79 S3C2500B PRODUCT OVERVIEW Table 1-21. S3C2500B Timer Controller Register Address Description Reset Value TMOD 0xF0040000 Timer mode register 0x00000000 0xF0040004 Timer Interrupt Clear 0x00000000 0xF0040008 Watchdog Timer Register 0x00000000 TDATA0 0xF0040010 Timer 0 data register 0x00000000 TCNT0 0xF0040014 Timer 0 count register...
Page 80 PRODUCT OVERVIEW S3C2500B NOTES 1-46...
Page 81: Programmer's Model
S3C2500B PROGRAMMER′ ′ S MODEL 2.1 OVERVIEW S3C2500B was developed using the advanced ARM9TDMI core designed by advanced RISC machines, Ltd. — Processor Operating States From the programmer′s point of view, the ARM9TDMI can be in one of two states: —...
Page 82: Memory Formats
Word is addressed by byte address of most significant byte. Figure 2-1. Big-Endian Addresses of Bytes within Words NOTE The data locations in the external memory are different with Figure 2-1 in the S3C2500B. Please refer to the chapter 4, system manager. 2.3.2 LITTLE-ENDIAN FORMAT In Little-Endian format, the lowest numbered byte in a word is considered the word′s least significant byte, and...
Page 83: Instruction Length
PROGRAMMER′ ′ S MODEL S3C2500B 2.4 INSTRUCTION LENGTH Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). 2.5 DATA TYPES ARM9TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four- byte boundaries and half words to two-byte boundaries.
Page 84: Registers
PROGRAMMER′ ′ S MODEL S3C2500B 2.7 REGISTERS ARM9TDMI has a total of 37 registers-31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. The processor state and operating mode dictate which registers are available to the programmer.
Page 85 PROGRAMMER′ ′ S MODEL S3C2500B ARM State General Registers and Program Counter System & User Supervisor About Undefined R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_svc R13_abt R13_irq R13_und R13_fiq R14_svc R14_abt R14_irq R14_und R14_fiq R15 (PC) R15 (PC) R15 (PC) R15 (PC)
Page 86 PROGRAMMER′ ′ S MODEL S3C2500B 2.7.2 The THUMB State Register Set The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0–R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR.
Page 87: The Relationship Between Arm And Thumb State Registers
PROGRAMMER′ ′ S MODEL S3C2500B 2.7.3 THE RELATIONSHIP BETWEEN ARM AND THUMB STATE REGISTERS The THUMB state registers relate to the ARM state registers in the following way: — THUMB state R0–R7 and ARM state R0–R7 are identical — THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical —...
Page 88: Accessing Hi-Registers In Thumb State
PROGRAMMER′ ′ S MODEL S3C2500B 2.7.4 ACCESSING HI-REGISTERS IN THUMB STATE In THUMB state, registers R8–R15 (the Hi registers) are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage.
Page 89: The Condition Code Flags
PROGRAMMER′ ′ S MODEL S3C2500B 2.8.1 THE CONDITION CODE FLAGS The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed.
Page 90 PROGRAMMER′ ′ S MODEL S3C2500B Table 2-1. PSR Mode. Bit Values M[4:0] Mode Visible THUMB State Registers Visible ARM State Registers 10000 User R7..R0, R14..R0, LR, SP PC, CPSR PC, CPSR 10001 R7..R0, R7..R0, LR_fiq, SP_fiq R14_fiq..R8_fiq, PC, CPSR, SPSR_fiq...
Page 91: Exceptions
PROGRAMMER′ ′ S MODEL S3C2500B 2.9 EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished.
Page 92: Exception Entry/Exit Summary
PROGRAMMER′ ′ S MODEL S3C2500B 2.9.3 EXCEPTION ENTRY/EXIT SUMMARY Table 2-2 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler. Table 2-2. Exception Entry/Exit Return Instruction Previous State...
Page 93: Irq
PROGRAMMER′ ′ S MODEL S3C2500B 2.9.5 IRQ The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting the I bit in the CPSR, though this can only be done from a privileged (non-User) mode.
Page 94: Software Interrupt
PROGRAMMER′ ′ S MODEL S3C2500B 2.9.7 SOFTWARE INTERRUPT The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or...
Page 95: Exception Priorities
PROGRAMMER′ ′ S MODEL S3C2500B 2.10.1 EXCEPTION PRIORITIES When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1. Reset 2. Data abort 3. FIQ 4. IRQ 5. Prefetch abort Lowest priority: 6.
Page 96: Interrupt Latencies
PROGRAMMER′ ′ S MODEL S3C2500B 2.11 INTERRUPT LATENCIES The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchroniser (Tsyncmax if asynchronous), plus the time for the longest instruction to complete (Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data abort entry (Texc), plus the time for FIQ entry (Tfiq).
Page 97: Introduction For Arm940T
PROGRAMMER′ ′ S MODEL S3C2500B 2.13 INTRODUCTION FOR ARM940T The ARM940T cached processor macrocell is a member of the ARM9 Thumb Family of high-performance 32-bit system-on-a-chip processor solutions. It is targeted at a wide range of embedded control applications where high performance, low system cost, small die size, and low power are key considerations.
Page 98: Arm940T Block Diagram
PROGRAMMER′ ′ S MODEL S3C2500B 2.14 ARM940T BLOCK DIAGRAM CPID[31:0] CPDIN[31:0] CPDOUT[31:0] IA[31:0] DA[31:0] Coprocessor Interface ID[31:0] DD[31:0] Protection Unit I Cache D Cache CP15 Control Control Instruction Data ARM9TDMI Cache Cache Processor Core (Integral EmbeddedICE) JTAG Interface[4:0] AMBA Interface...
Page 99: About The Arm940T Programmer's Model
PROGRAMMER′ ′ S MODEL S3C2500B 2.15 ABOUT THE ARM940T PROGRAMMER'S MODEL The ARM940T cached processor macrocell includes the ARM9TDMI microprocessor core, instruction and data caches, a write-buffer, and a protection unit for defining the attributes of regions of memory. The ARM940T incorporates two coprocessors: •...
Page 100: Data Abort Model
PROGRAMMER′ ′ S MODEL S3C2500B 2.15.1 DATA ABORT MODEL The base restored data abort model differs from the base updated data abort model implemented by ARM7TDMI. The difference in the data abort model affects only a very small section of operating system code, the data abort handler.
Page 101: Arm940T Cp15 Registers
PROGRAMMER′ ′ S MODEL S3C2500B 2.16 ARM940T CP15 REGISTERS 2.16.1 CP15 REGISTER MAP SUMMARY The ARM940T incorporates CP15 for system control. The register map for C15 is shown in Table 2-5. Table 2-5. CP15 Register Map Register Function Access ID code/Cache type...
Page 102 PROGRAMMER′ ′ S MODEL S3C2500B 2.16.1.2 Register 0: Cache type This is a read-only register which allows operating systems to establish how to perform operations such as cache cleaning and lockdown. Future ARM cached processors will contain this register, allowing RTOS vendors to produce future-proof versions of their operating systems.
Page 103 PROGRAMMER′ ′ S MODEL S3C2500B 2.16.1.3 Register 1: Control register This contains the global control bits of the ARM940T. All reserved bits should either be written with zero or one, as indicated, or written using read-modify-write. The reserved bits have an unpredictable value when read.
Page 104 PROGRAMMER′ ′ S MODEL S3C2500B 2.16.1.4 Register 2: Instruction and data cacheable registers This location provides access to two registers which contain the cacheable attributes for each of eight memory areas. The two registers provide individual control for the I and D address spaces. The opcode_2 field determines whether the instruction-or data-cacheable attributes are programmed: If the opcode_2 field = 0, the data-cacheable bits are programmed.
Page 105 PROGRAMMER′ ′ S MODEL S3C2500B 2.16.1.5 Register 3: Write buffer control register This register contains a write buffer control (bufferable) attribute bit for each of the eight areas of memory. Each bit is used in conjunction with the cacheable bit to control write-buffer operation. For a description of buffer behavior, see The write buffer on page 4-11.
Page 106 PROGRAMMER′ ′ S MODEL S3C2500B Each register contains the access permission bits, apn[1:0], for the eight areas of instruction or data memory, as shown in Table 2-12. All defined bits in the control register are set to zero at reset.
Page 107 PROGRAMMER′ ′ S MODEL S3C2500B 2.16.1.7 Register 6: Protection region base and size registers This register is used to define 16 programmable regions (eight instruction, eight data) in memory. These registers define the base and size of each of the eight areas of memory. Individual control is provided for the instruction and data memory regions.
Page 108 PROGRAMMER′ ′ S MODEL S3C2500B Each protection region register has the format shown in Table 2-16. Table 2-16. CP15 Protection Region Register Format Register bit Function 31:12 Base address 11:6 Unused Area size (See Table 2-17) Region enable. Reset to disable (0).
Page 109 PROGRAMMER′ ′ S MODEL S3C2500B 2.16.1.8 Register 7: Cache operations A write to this register can be used to perform the following operations: • Flush ICache and Dcache • Prefetch an ICache line • Wait for interrupt • Drain the write buffer •...
Page 110 PROGRAMMER′ ′ S MODEL S3C2500B 2.16.1.8.1 Index/Segment Format Where the required value is an index/segment, the format is: Table 2-19. CP15 Register 7 Index/Segment Data Format Rd bit position Function 31:26 Index 25:6 Should be zero Segment Should be zero 2.16.1.8.2 ICache Prefetch Data Format...
Page 111 PROGRAMMER′ ′ S MODEL S3C2500B 2.16.1.8.4 Drain Write Buffer This CP15 operation causes instruction execution to be stalled until the write buffer is emptied. This operation is useful in real time applications where the processor needs to be sure that a write to a peripheral has completed before program execution continues.
Page 112 PROGRAMMER′ ′ S MODEL S3C2500B 2.16.1.10 Register 15: Test/debug register The DTRRobin and ITRRobin bits set the respective caches into a pseudo round-robin replacement mode. All defined bits in the control register are set to zero at reset. Table 2-22. CP15 Register 15...
Page 113: Chapter 3 Instruction Set
S3C2500B INSTRUCTION SET INSTRUCTION SET 3.1 INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set and the THUMB instruction set in the ARM9TDMI core. 3.1.1 FORMAT SUMMARY The ARM instruction set formats are shown below. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
Page 114: Instruction Summary
INSTRUCTION SET S3C2500B 3.1.2 INSTRUCTION SUMMARY Table 3-1. The ARM Instruction Set Mnemonic Instruction Action Add with carry Rd: = Rn + Op2 + Carry Rd: = Rn + Op2 Rd: = Rn AND Op2 Branch R15: = address Bit clear...
Page 115 S3C2500B INSTRUCTION SET Table 3-1. The ARM Instruction Set (Continued) Mnemonic Instruction Action Rd: = Rn OR Op2 Reverse subtract Rd: = Op2 - Rn Reverse subtract with carry Rd: = Op2 - Rn-1 + Carry Subtract with carry Rd: = Rn - Op2-1 + Carry...
Page 116: The Condition Field
INSTRUCTION SET S3C2500B 3.2 THE CONDITION FIELD In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction′s condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be executed.
Page 117: Branch And Exchange (Bx)
S3C2500B INSTRUCTION SET 3.3 BRANCH AND EXCHANGE (BX) This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. This instruction performs a branch by copying the contents of a general register, Rn, into the program counter, PC.
Page 118 INSTRUCTION SET S3C2500B Examples R0, Into_THUMB + 1 ; Generate branch target address ; and set bit 0 high - hence ; arrive in THUMB state. ; Branch and change to THUMB ; state. CODE16 ; Assemble subsequent code as Into_THUMB ;...
Page 119: Branch And Branch With Link (B, Bl)
S3C2500B INSTRUCTION SET 3.4 BRANCH AND BRANCH WITH LINK (B, BL) The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction encoding is shown in Figure 3-3, below. Cond Offset [24] Link Bit...
Page 120: Assembler Syntax
INSTRUCTION SET S3C2500B 3.4.3 ASSEMBLER SYNTAX Items in {} are optional. Items in < > must be present. B{L}{cond} <expression> Used to request the branch with link form of the instruction. If absent, R14 will not be affected by the instruction.
Page 121: Data Processing
S3C2500B INSTRUCTION SET 3.5 DATA PROCESSING The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-4. 26 25 Opcode Cond Operand2 [15:12] Destination Register...
Page 122 INSTRUCTION SET S3C2500B The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. The first operand is always a register (Rn). The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction.
Page 123: Cpsr Flags
S3C2500B INSTRUCTION SET 3.5.1 CPSR FLAGS The data processing operations may be classified as logical or arithmetic. The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to produce the result.
Page 124: Shifts
INSTRUCTION SET S3C2500B 3.5.2 SHIFTS When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right).
Page 125 S3C2500B INSTRUCTION SET Contents of Rm carry out Value of Operand 2 Figure 3-7. Logical Shift Right The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is the same as logical shift left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow LSR #32 to be specified.
Page 126 INSTRUCTION SET S3C2500B Rotate right (ROR) operations reuse the bits which overshoot in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. For example, ROR #5 is shown in Figure 3-9.
Page 127 S3C2500B INSTRUCTION SET 3.5.2.2 Register Specified Shift Amount Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any general register other than R15. If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the CPSR C flag will be passed on as the shifter carry output.
Page 128: Immediate Operand Rotates
INSTRUCTION SET S3C2500B 3.5.3 IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value. This value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field.
Page 129: Instruction Cycle Times
S3C2500B INSTRUCTION SET 3.5.7 INSTRUCTION CYCLE TIMES Data processing instructions vary in the number of incremental cycles taken as follows: Table 3-4. Incremental Cycle Times Processing Type Cycles Normal data processing Data processing with register specified shift 1S + 1I...
Page 130 INSTRUCTION SET S3C2500B Examples ADDEQ R2,R4,R5 ; If the Z flag is set make R2: = R4 + R5 TEQS R4,#3 ; Test R4 for equality with 3. ; (The S is in fact redundant as the ; assembler inserts it automatically.) R4,R5,R7,LSR R2 ;...
Page 131: Psr Transfer (Mrs, Msr)
S3C2500B INSTRUCTION SET 3.6 PSR TRANSFER (MRS, MSR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The MRS and MSR instructions are formed from a subset of the data processing operations and are implemented using the TEQ, TST, CMN and CMP instructions without the S flag set.
Page 132 INSTRUCTION SET S3C2500B MRS (Transfer PSR Contents to a Register) 00010 001111 Cond 000000000000 [15:21] Destination Register [19:16] Source PSR 0 = CPSR 1 = SPSR_<current mode> [31:28] Condition Field MRS (Transfer Register Contents to PSR) 00010 101001111 Cond 00000000...
Page 133: Reserved Bits
S3C2500B INSTRUCTION SET 3.6.2 RESERVED BITS Only twelve bits of the PSR are defined in ARM9TDMI (N, Z, C, V, I, F, T & M[4:0]); the remaining bits are reserved for use in future versions of the processor. Refer to Figure 2-6 for a full description of the PSR bits.
Page 134: Assembler Syntax
INSTRUCTION SET S3C2500B 3.6.4 ASSEMBLER SYNTAX — MRS - transfer PSR contents to a register MRS{cond} Rd,<psr> — MSR - transfer register contents to PSR MSR{cond} <psr>,Rm — MSR - transfer register contents to PSR flag bits only MSR{cond} <psrf>,Rm The most significant four bits of the register contents are written to the N,Z,C &...
Page 135: Multiply And Multiply-Accumulate (Mul, Mla)
S3C2500B INSTRUCTION SET 3.7 MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-12. The multiply and multiply-accumulate instructions use an 8 bit Booth's algorithm to perform integer multiplication.
Page 136: Cpsr Flags
INSTRUCTION SET S3C2500B 3.7.1 CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z (Zero) flags are set correctly on the result (N is made equal to bit 31 of the result, and Z is set if and only if the result is zero).
Page 137: Multiply Long And Multiply-Accumulate Long (Mull,Mlal)
S3C2500B INSTRUCTION SET 3.8 MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL,MLAL) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-13. The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results.
Page 138: Cpsr Flags
INSTRUCTION SET S3C2500B 3.8.2 CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N and Z flags are set correctly on the result (N is equal to bit 63 of the result, Z is set if and only if all 64 bits of the result are zero).
Page 139: Assembler Syntax
S3C2500B INSTRUCTION SET 3.8.4 ASSEMBLER SYNTAX Table 3-5. Assembler Syntax Descriptions Mnemonic Description Purpose UMULL{cond}{S} RdLo, RdHi, Rm, Rs Unsigned multiply long 32 x 32 = 64 UMLAL{cond}{S} RdLo, RdHi, Rm, Rs Unsigned multiply & Accumulate long 32 x 32 + 64 = 64...
Page 140: Single Data Transfer (Ldr, Str)
INSTRUCTION SET S3C2500B 3.9 SINGLE DATA TRANSFER (LDR, STR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-14. The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register.
Page 141: Offsets And Auto-Indexing
S3C2500B INSTRUCTION SET 3.9.1 OFFSETS AND AUTO-INDEXING The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). The offset may be added to (U = 1) or subtracted from (U = 0) the base register Rn.
Page 142 INSTRUCTION SET S3C2500B Memory Register LDR from word aligned address Memory Register LDR from address offset by 2 Figure 3-15. Little-Endian Offset Addressing 3.9.3.2 Big-Endian Configuration A byte load (LDRB) expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary, on data bus inputs 23 through 16 if it is a word address plus one byte, and so on.
Page 143: Use Of R15
S3C2500B INSTRUCTION SET 3.9.4 USE OF R15 Write-back must not be specified if R15 is specified as the base register (Rn). When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction.
Page 144: Assembler Syntax
INSTRUCTION SET S3C2500B 3.9.8 ASSEMBLER SYNTAX <LDR|STR>{cond}{B}{T} Rd,<Address> where: Load from memory into a register Store from a register into memory {cond} Two-character condition mnemonic. See Table 3-2. If B is present then byte transfer, otherwise word transfer If T is present the W bit will be set in a post-indexed instruction, forcing non- privileged mode for the transfer cycle.
Page 145 S3C2500B INSTRUCTION SET Examples R1,[R2,R4]! ; Store R1 at R2 + R4 (both of which are registers) ; and write back address to R2. R1,[R2],R4 ; Store R1 at R2 and write back R2 + R4 to R2. R1,[R2,#16] ; Load R1 from contents of R2 + 16, but don't write back.
Page 146: Halfword And Signed Data Transfer (Ldrh/Strh/Ldrsb/Ldrsh)
INSTRUCTION SET S3C2500B 3.10 HALFWORD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-16. These instructions are used to load or store half-words of data and also load sign-extended bytes or half-words of data.
Page 147: Offsets And Auto-Indexing
S3C2500B INSTRUCTION SET 8 7 6 5 4 3 Cond Offset S H 1 Offset [3:0] Immediate Offset (Low Nibble) [6][5] S H 0 0 = SWP instruction 0 1 = Unsigned halfwords 1 1 = Signed byte 1 1 = Signed half words...
Page 148: Half-Word Load And Stores
INSTRUCTION SET S3C2500B 3.10.2 HALF-WORD LOAD AND STORES Setting S = 0 and H = 1 may be used to transfer unsigned Half-words between an ARM9TDMI register and memory. The action of LDRH and STRH instructions is influenced by the BIGEND control signal. The two possible configurations are described in the section below.
Page 149: Use Of R15
S3C2500B INSTRUCTION SET 3.10.4.2 Big-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte.
Page 150: Assembler Syntax
INSTRUCTION SET S3C2500B 3.10.8 ASSEMBLER SYNTAX <LDR|STR>{cond}<H|SH|SB> Rd,<address> Load from memory into a register Store from a register into memory {cond} Two-character condition mnemonic. See Table 3-2. Transfer half-word quantity Load sign extended byte (Only valid for LDR) Load sign extended half-word (Only valid for LDR) An expression evaluating to a valid register number.
Page 151 S3C2500B INSTRUCTION SET Examples LDRH R1,[R2,-R3]! ; Load R1 from the contents of the half-word address ; contained in R2-R3 (both of which are registers) ; and write back address to R2 STRH R3,[R4,#14] ; Store the half-word in R3 at R14+14 but don't write back.
Page 152: Block Data Transfer (Ldm, Stm)
INSTRUCTION SET S3C2500B 3.11 BLOCK DATA TRANSFER (LDM, STM) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-18. Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible registers.
Page 153: Addressing Modes
S3C2500B INSTRUCTION SET 3.11.2 ADDRESSING MODES The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the up/ down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last.
Page 154 INSTRUCTION SET S3C2500B 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 Figure 3-20. Pre-Increment Addressing 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 Figure 3-21. Post-Decrement Addressing 3-42...
Page 155: Use Of The S Bit
S3C2500B INSTRUCTION SET 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 Figure 3-22. Pre-Decrement Addressing 3.11.4 USE OF THE S BIT When the S bit is set in a LDM/STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction.
Page 156: Inclusion Of The Base In The Register List
INSTRUCTION SET S3C2500B 3.11.6 INCLUSION OF THE BASE IN THE REGISTER LIST When write-back is specified, the base is written back at the end of the second cycle of the instruction. During a STM, the first register is written out at the start of the second cycle. A STM which includes storing the base, with the base as the first register to be stored, will therefore store the unchanged value, whereas with the base second or later in the transfer order, will store the modified value.
Page 157: Assembler Syntax
S3C2500B INSTRUCTION SET 3.11.9 ASSEMBLER SYNTAX <LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{^} where: {cond} Two character condition mnemonic. See Table 3-2. An expression evaluating to a valid register number <Rlist> A list of registers and register ranges enclosed in {} (e.g. {R0, R2–R7, R10}).
Page 158 INSTRUCTION SET S3C2500B Examples LDMFD SP!,{R0,R1,R2} ; Unstack 3 registers. STMIA R0,{R0-R15} ; Save all registers. LDMFD SP!,{R15} ; R15 <- (SP), CPSR unchanged. LDMFD SP!,{R15}^ ; R15 <- (SP), CPSR <- SPSR_mode ; (allowed only in privileged modes). STMFD R13,{R0-R14}^ ;...
Page 159: Single Data Swap (Swp)
S3C2500B INSTRUCTION SET 3.12 SINGLE DATA SWAP (SWP) Cond 00010 0000 1001 [3:0] Source Register [15:12] Destination Register [19:16] Base Register [22] Byte/Word Bit 0 = Swap word quantity 1 = Swap word quantity [31:28] Condition Field Figure 3-23. Swap Instruction The instruction is only executed if the condition is true.
Page 160: Data Aborts
INSTRUCTION SET S3C2500B 3.12.3 DATA ABORTS If the address used for the swap is unacceptable to a memory management system, the memory manager can flag the problem by driving ABORT HIGH. This can happen on either the read or the write cycle (or both), and in either case, the data abort trap will be taken.
Page 161: Software Interrupt (Swi)
S3C2500B INSTRUCTION SET 3.13 SOFTWARE INTERRUPT (SWI) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-24, below 1111 Cond Comment Field (Ignored by Processor) [31:28] Condition Field Figure 3-24.
Page 162: Assembler Syntax
INSTRUCTION SET S3C2500B 3.13.4 ASSEMBLER SYNTAX SWI{cond} <expression> {cond} Two character condition mnemonic, Table 3-2. <expression> Evaluated and placed in the comment field (which is ignored by ARM9TDMI). Examples ReadC ; Get next character from read stream. WriteI+ “k” ; Output a “k” to the write stream.
Page 163: Coprocessor Data Operations (Cdp)
So then all coprocessor instructions will cause the undefined instruction trap to be taken on the S3C2500B. These coprocessor instructions can be emulated by the undefined trap handler. Even though external coprocessor can not be connected to the S3C2500B, the coprocessor instructions are still described here in full for completeness.
Page 164: Instruction Cycle Times
INSTRUCTION SET S3C2500B 3.14.3 INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S + bI incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. S and I are defined as sequential (S-cycle) and internal (I-cycle).
Page 165: Coprocessor Data Transfers (Ldc, Stc)
S3C2500B INSTRUCTION SET 3.15 COPROCESSOR DATA TRANSFERS (LDC, STC) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-26. This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessor's registers directly to memory.
Page 166: Addressing Modes
INSTRUCTION SET S3C2500B 3.15.2 ADDRESSING MODES ARM9TDMI is responsible for providing the address used by the memory system for the transfer, and the addressing modes available are a subset of those used in single data transfer instructions. Note, however, that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers, whereas they are 12 bits wide and specify byte offsets for single data transfers.
Page 167: Assembler Syntax
S3C2500B INSTRUCTION SET 3.15.7 ASSEMBLER SYNTAX <LDC|STC>{cond}{L} p#,cd,<Address> Load from memory to coprocessor Store from coprocessor to memory When present perform long transfer (N = 1), otherwise perform short transfer (N = 0) {cond} Two character condition mnemonic. See Table 3-2.
Page 168: Coprocessor Register Transfers (Mrc, Mcr)
INSTRUCTION SET S3C2500B 3.16 COPROCESSOR REGISTER TRANSFERS (MRC, MCR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.. The instruction encoding is shown in Figure 3-27. This class of instruction is used to communicate information directly between ARM9TDMI and a coprocessor. An...
Page 169: Transfers To R15
S3C2500B INSTRUCTION SET 3.16.2 TRANSFERS TO R15 When a coprocessor register transfer to ARM9TDMI has R15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the N, Z, C and V flags respectively. The other bits of the transferred word are ignored, and the PC and other CPSR bits are unaffected by the transfer.
Page 170: Undefined Instruction
INSTRUCTION SET S3C2500B 3.17 UNDEFINED INSTRUCTION The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction format is shown in Figure 3-28. 25 24 5 4 3 xxxxxxxxxxxxxxxxxxxx xxxx Cond Figure 3-28.
Page 171: Instruction Set Examples
S3C2500B INSTRUCTION SET 3.18 INSTRUCTION SET EXAMPLES The following examples show ways in which the basic ARM9TDMI instructions can combine to give efficient code. None of these methods saves a great deal of execution time (although they may save some), mostly they just save code.
Page 172 INSTRUCTION SET S3C2500B Division and Remainder A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross development toolkit, available from your supplier. A short general purpose divide routine follows.
Page 173: Pseudo-Random Binary Sequence Generator
S3C2500B INSTRUCTION SET 5. Overflow in unsigned multiply accumulate with a 64 bit result UMULL Rl,Rh,Rm,Rn ; 3 to 6 cycles ADDS Rl,Rl,Ra1 ; Lower accumulate Rh,Rh,Ra2 ; Upper accumulate overflow ; 1 cycle and 2 registers 6. Overflow in signed multiply accumulate with a 64 bit result...
Page 174 INSTRUCTION SET S3C2500B Multiplication by 6 Ra,Ra,Ra,LSL #1 ; Multiply by 3 Ra,Ra,LSL#1 ; and then by 2 Multiply by 10 and add in extra number Ra,Ra,Ra,LSL#2 ; Multiply by 5 Ra,Rc,Ra,LSL#1 ; Multiply by 2 and add in next digit General recursive method for Rb := Ra*C, C a constant: 1.
Page 175: Loading A Word From An Unknown Alignment
S3C2500B INSTRUCTION SET 3.18.4 LOADING A WORD FROM AN UNKNOWN ALIGNMENT ; Enter with address in Ra (32 bits) uses ; Rb, Rc result in Rd. Note d must be less than c e.g. 0,1 Rb,Ra,#3 ; Get word aligned address...
Page 176: Thumb Instruction Set Format
INSTRUCTION SET S3C2500B 3.19 THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16-bit versions of ARM instruction sets (32-bit format). The ARM instructions are reduced to 16-bit versions, Thumb instructions, at the cost of versatile functions of the ARM instruction sets. The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM9TDMI core.
Page 177: Opcode Summary
S3C2500B INSTRUCTION SET 3.19.2 OPCODE SUMMARY The following table summarises the THUMB instruction set. For further information about a particular instruction please refer to the sections listed in the right-most column. Table 3-7. THUMB Instruction Set Opcodes Mnemonic Instruction Lo-Register...
Page 178 INSTRUCTION SET S3C2500B Table 3-7. THUMB Instruction Set Opcodes (Continued) Mnemonic Instruction Lo-Register Hi-Register Condition Operand Operand Codes Set Subtract with carry – STMIA Store multiple – – Store word – – STRB Store byte – – STRH Store half-word –...
Page 179: Format 1: Move Shifted Register
S3C2500B INSTRUCTION SET 3.20 FORMAT 1: MOVE SHIFTED REGISTER Offset5 [2:0] Destination Register [5:3] Source Register [10:6] Immediate Vale [12:11] Opcode 0 = LSL 1 = LSR 2 = ASR Figure 3-30. Format 1 3.20.1 OPERATION These instructions move a shifted value between Lo registers. The THUMB assembler syntax is shown in Table 3-8.
Page 180: Format 2: Add/Subtract
INSTRUCTION SET S3C2500B 3.21 FORMAT 2: ADD/SUBTRACT Rn/Offset3 [2:0] Destination Register [5:3] Source Register [8:6] Register/Immediate Value [9] Opcode 0 = ADD 1 = SUB [10] Immediate Flag 0 = Register operand 1 = Immediate oerand Figure 3-31. Format 2 3.21.1 OPERATION...
Page 181: Instruction Cycle Times
S3C2500B INSTRUCTION SET 3.21.2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-9. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples R0, R3, R4 ;...
Page 182: Format 3: Move/Compare/Add/Subtract Immediate
INSTRUCTION SET S3C2500B 3.22 FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE Offset8 [7:0] Immediate Value [10:8] Source/Destination Register [12:11] Opcode 0 = MOV 1 = CMP 2 = ADD 3 = SUB Figure 3-32. Format 3 3.22.1 OPERATIONS The instructions in this group perform operations between a Lo register and an 8-bit immediate value. The THUMB assembler syntax is shown in Table 3-10.
Page 183: Format 4: Alu Operations
S3C2500B INSTRUCTION SET 3.23 FORMAT 4: ALU OPERATIONS [2:0] Source/Destination Register [5:3] Source Register 2 [9:6] Opcode Figure 3-33. Format 4 3.23.1 OPERATION The following instructions perform ALU operations on a Lo register pair. NOTE All instructions in this group set the CPSR condition codes Table 3-11.
Page 184: Instruction Cycle Times
INSTRUCTION SET S3C2500B 3.23.2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-11. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples R3, R4 ;...
Page 185: Format 5: Hi-Register Operations/Branch Exchange
S3C2500B INSTRUCTION SET 3.24 FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE Rs/Hs Rd/Hd [2:0] Destination Register [5:3] Source Register [6] Hi Operand Flag 2 [7] Hi Operand Flag 1 [9:8] Opcode Figure 3-34. Format 5 3.24.1 OPERATION There are four sets of instructions in this group. The first three allow ADD, CMP and MOV operations to be performed between Lo and Hi registers, or a pair of Hi registers.
Page 186: Instruction Cycle Times
INSTRUCTION SET S3C2500B Table 3-12. Summary of Format 5 Instructions OP H1 THUMB Assembler ARM Equivalent Action ADD Rd, Hs ADD Rd, Rd, Hs Add a register in the range 8-15 to a register in the range 0-7. ADD Hd, Rs...
Page 187: Using R15 As An Operand
S3C2500B INSTRUCTION SET Examples Hi-Register Operations PC, R5 ; PC := PC + R5 but don't set the condition codes.CMP R4, R12 ; Set the condition codes on the result of R4 - R12. R15, R14 ; Move R14 (LR) into R15 (PC) ;...
Page 188: Format 6: Pc-Relative Load
INSTRUCTION SET S3C2500B 3.25 FORMAT 6: PC-RELATIVE LOAD Word 8 [7:0] Immediate Value [10:8] Destination Register Figure 3-35. Format 6 3.25.1 OPERATION This instruction loads a word from an address specified as a 10-bit immediate offset from the PC. The THUMB assembler syntax is shown below.
Page 189: Format 7: Load/Store With Register Offset
S3C2500B INSTRUCTION SET 3.26 FORMAT 7: LOAD/STORE WITH REGISTER OFFSET [2:0] Source/Destination Register [5:3] Base Register [8:6] Offset Register [10] Byte/Word Flag 0 = Transfer word quantity 1 = Transfer byte quantity [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 3-36.
Page 190: Instruction Cycle Times
INSTRUCTION SET S3C2500B 3.26.2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-14. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples R3, [R2,R6] ;...
Page 191: Format 8: Load/Store Sign-Extended Byte/Half-Word
S3C2500B INSTRUCTION SET 3.27 FORMAT 8: LOAD/STORE SIGN-EXTENDED BYTE/HALF-WORD [2:0] Destination Register [5:3] Base Register [8:6] Offset Register [10] Sign-Extended Flag 0 = Operand not sing-extended 1 = Operand sing-extended [11] H Flag Figure 3-37. Format 8 3.27.1 OPERATION These instructions load optionally sign-extended bytes or half-words, and store half-words. The THUMB assembler syntax is shown below.
Page 192: Instruction Cycle Times
INSTRUCTION SET S3C2500B 3.27.2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-15. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples...
Page 193: Format 9: Load/Store With Immediate Offset
S3C2500B INSTRUCTION SET 3.28 FORMAT 9: LOAD/STORE WITH IMMEDIATE OFFSET Offset5 [2:0] Source/Destination Register [5:3] Base Register [10:6] Offset Register [11] Load/Store Flag 0 = Store to memory 1 = Load from memory [12] Byte/Word Flad 0 = Transfer word quantity 1 = Transfer byte quantity Figure 3-38.
Page 194: Instruction Cycle Times
INSTRUCTION SET S3C2500B 3.28.2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-16. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples R2, [R5,#116] ;...
Page 195: Format 10: Load/Store Half-Word
S3C2500B INSTRUCTION SET 3.29 FORMAT 10: LOAD/STORE HALF-WORD Offset5 [2:0] Source/Destination Register [5:3] Base Register [10:6] Immediate Value [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 3-39. Format 10 3.29.1 OPERATION These instructions transfer half-word values between a Lo register and memory. Addresses are pre-indexed, using a 6-bit immediate value.
Page 196: Format 11: Sp-Relative Load/Store
INSTRUCTION SET S3C2500B 3.30 FORMAT 11: SP-RELATIVE LOAD/STORE Word 8 [7:0] Immediate Value [10:8] Destination Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 3-40. Format 11 3.30.1 OPERATION The instructions in this group perform an SP-relative load or store. The THUMB assembler syntax is shown in the following table.
Page 197: Format 12: Load Addres
S3C2500B INSTRUCTION SET 3.31 FORMAT 12: LOAD ADDRES Word 8 [7:0] 8-bit Unsigned Constant [10:8] Destination Register [11] Source 0 = PC 1 = SP Figure 3-41. Format 12 3.31.1 OPERATION These instructions calculate an address by adding an 10-bit constant to either the PC or the SP, and load the resulting address into a register.
Page 198: Instruction Cycle Times
INSTRUCTION SET S3C2500B 3.31.2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-19. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples R2, PC, #572 ;...
Page 199: Format 13: Add Offset To Stack Pointer
S3C2500B INSTRUCTION SET 3.32 FORMAT 13: ADD OFFSET TO STACK POINTER SWord 7 [6:0] 7-bit Immediate Value [7] Sign Flag 0 = Offset is positive 1 = Offset is negative Figure 3-42. Format 13 3.32.1 OPERATION This instruction adds a 9-bit signed constant to the stack pointer. The following table shows the THUMB assembler syntax.
Page 200: Format 14: Push/Pop Registers
INSTRUCTION SET S3C2500B 3.33 FORMAT 14: PUSH/POP REGISTERS Rlist [7:0] Register List [8] PC/LR Bit 0 = Do not store LR/Load PC 1 = Store LR/Load PC [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 3-43.
Page 201: Instruction Cycle Times
S3C2500B INSTRUCTION SET 3.33.2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-21. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples PUSH {R0–R4,LR}...
Page 202: Format 15: Multiple Load/Store
INSTRUCTION SET S3C2500B 3.34 FORMAT 15: MULTIPLE LOAD/STORE Rlist [7:0] Register List [10:8] Base Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 3-44. Format 15 3.34.1 OPERATION These instructions allow multiple loading and storing of Lo registers. The THUMB assembler syntax is shown in the following table.
Page 203: Format 16: Conditional Branch
S3C2500B INSTRUCTION SET 3.35 FORMAT 16: CONDITIONAL BRANCH Cond SOffset 8 [7:0] 8-bit Signed Immediate [11:8] Condition Figure 3-45. Format 16 3.35.1 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes.
Page 204: Instruction Cycle Times
INSTRUCTION SET S3C2500B Table 3-23. The Conditional Branch Instructions (Continued) Code THUMB ARM Equivalent Action Assembler 1011 BLT label BLT label Branch if N set and V clear, or N clear and V set (less than) 1100 BGT label BGT label...
Page 205: Format 17: Software Interrupt
S3C2500B INSTRUCTION SET 3.36 FORMAT 17: SOFTWARE INTERRUPT Value 8 [7:0] Comment Field Figure 3-46. Format 17 3.36.1 OPERATION The SWI instruction performs a software interrupt. On taking the SWI, the processor switches into ARM state and enters Supervisor (SVC) mode.
Page 206: Format 18: Unconditional Branch
INSTRUCTION SET S3C2500B 3.37 FORMAT 18: UNCONDITIONAL BRANCH Offset11 [10:0] Immediate Value Figure 3-47. Format 18 3.37.1 OPERATION This instruction performs a PC-relative Branch. The THUMB assembler syntax is shown below. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction.
Page 207: Format 19: Long Branch With Link
S3C2500B INSTRUCTION SET 3.38 FORMAT 19: LONG BRANCH WITH LINK Offset [10:0] Long Branch and Link Offset High/Low [11] Low/High Offset Bit 0 = Offset high 1 = Offset low Figure 3-48. Format 19 3.38.1 OPERATION This format specifies a long branch with link.
Page 208: Instruction Cycle Times
INSTRUCTION SET S3C2500B 3.38.2 INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction. Table 3-26. The BL Instruction THUMB Assembler ARM Equivalent Action BL label none LR := PC + OffsetHigh << 12 temp := next instruction address PC := LR + OffsetLow <<...
Page 209: Instruction Set Examples
S3C2500B INSTRUCTION SET 3.39 INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code. Each example also shows the ARM equivalent so these may be compared. 3.39.1 MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following shows code to multiply by various constants using 1, 2 or 3 Thumb instructions alongside the ARM equivalents.
Page 210: General Purpose Signed Divide
INSTRUCTION SET S3C2500B 3.39.2 GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code. 3.39.2.1 Thumb code ;signed_divide ; Signed divide of R1 by R0: returns quotient in R0, ;...
Page 211 S3C2500B INSTRUCTION SET 3.39.2.2 ARM Code signed_divide ; Effectively zero a4 as top bit will be shifted out later ANDS a4, a1, #&80000000 RSBMI a1, a1, #0 EORS ip, a4, a2, ASR #32 ;ip bit 31 = sign of result ;ip bit 30 = sign of a2...
Page 212: Division By A Constant
INSTRUCTION SET S3C2500B 3.39.3 DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code.
Page 213: System Configuration
S3C2500B SYSTEM CONFIGURATION SYSTEM CONFIGURATION 4.1 OVERVIEW The System Configuration consists of several functions that control the clock configuration, system bus arbitration method and address remap function etc. 4.2 FEATURES Key features of the system configuration include the following; •...
Page 214: Address Map
EXT I/O Bank #0 0x00000000 Figure 4-1. S3C2500B Address map after resest Each memory block is mapped within the fixed location of memory space. As shown in the figure 4-1, the maximum size of ROM/SRAM/Flash/External IO bank is restricted to 16M-bytes and the SDRAM bank can be mapped within 1G-byte memory space.
Page 215: Remap Of Memory Space
4.5 EXTERNAL ADDRESS TRANSLATION The S3C2500B address bus is , in some respects, different than the bus used in other standard CPUs. Based on the required data bus width of each memory bank, the internal system address bus is shifted out to an external address bus, ADDR[23:0].
Page 216: Arbitration Scheme
The S3C2500B can support the fixed priority and the round-robin method for AHB bus arbitration by register setting. Especially, the S3C2500B can program the priority order in the fixed priority mode as well as the ratio of the bus occupancy in the round-robin priority mode.
Page 217 Controller 1 HDLC Controller 0 Figure 4-3. Priority Groups of S3C2500B AHB Bus Programmable Priority Register are HPRIF(Programmable Priority Register for Fixed) and HPRIR (Programmable Priority Register for Round-Robin). If system configuration register (0xF0000000) SYSCFG[0] = 0x1, the programmable fixed priority is run by HPRIF register.
Page 218 SYSTEM CONFIGURATION S3C2500B SYSCFG [0] System bus arbitration method (ARB) 0 = Round-robin 1 = Fixed priority NOTE: See page 4-16 and 4-17. HPRIF 16 15 12 11 Reserved hprif4 hprif3 hprif1 hprif5 hprif2 hprif0 Low Priority High Priority HPRIR...
Page 219: Problem Solvings With Programmable Round-Robin
Ethernet controller 0 1/6, and Ethernet controller 1 1/6. In short, GDMA is run four times more than Ethernet controller 0 and 1. This is because S3C2500B is designed to turn the bus occupancy to the next master when there is non-used master. For instance,...
Page 220 SYSTEM CONFIGURATION S3C2500B The following is the problem solving with software. HPRIR Channel Expected Real HPRIR Channel Occupancy System Bus Occupancy Occupancy GDMA GDMA Ethernet Ethernet controller 0 controller 0 ⇒ Ethernet Ethernet controller 1 controller 1 Problem Problem Solving Writing "0x000330", instead of "0x0"...
Page 221: Clock Configuration
4.7 CLOCK CONFIGURATION The S3C2500B has four PLL clocking scheme – CPU PLL, System BUS PLL, USB PLL, PHY PLL. All of the PLL can operate if the corresponding clock select pin is set to “0” (CLKSEL- shared with CPU PLL and System BUS PLL, USB_CLKSEL, PHY_CLKSEL).
Page 222 SYSTEM CONFIGURATION S3C2500B Table 4-3. Clock Frequencies for CLKMOD Pins, CPU_FREQ Pins, and BUS_FREQ Pins (Continued) CLKMOD [1:0] CPU_FREQ [2:0] BUS_FREQ [2:0] ARM940T Clock AMBA BUS Clock USB Clock Frequency Frequency Frequency 2'b11 (Async) 3'b001 3'b000 150MHz 133MHz 48MHz 3'b001...
Page 223 S3C2500B SYSTEM CONFIGURATION Table 4-3. Clock Frequencies for CLKMOD Pins, CPU_FREQ Pins, and BUS_FREQ Pins (Continued) CLKMOD [1:0] CPU_FREQ [2:0] BUS_FREQ [2:0] ARM940T Clock AMBA BUS Clock USB Clock Frequency Frequency Frequency 2'b11 (Async) 3'b101 3'b000 66MHz 133MHz 48MHz 3'b101...
Page 224 Where the Fin is the frequency of the PLL input clock and the Fout is the frequency of the PLL output clock. The four PLLs in the S3C2500B are controlled by above formula and the table 4-4 shows the PLL variables for the most widely used frequencies.
Page 225 Table 3. The CLKCON[15:0] register can divide the various AMBA clock frequecies of the Table 4-3. All PLL can be controlled by either pin setting or register setting. Figure 4-5. Shows the Clock Generation Logic of the S3C2500B 4-13...
Page 226: External Bus Master
SYSTEM CONFIGURATION S3C2500B 4.8 EXTERNAL BUS MASTER The S3C2500 allows the external bus master to get the external memory bus and control the external memory system. When the external bus master asserts XBMREQ to get the external memory bus, the S3C2500 asserts XMBACK high and drives the state of the external memory bus to high impedance after S3C2500 finishes current transfer with memory.
Page 227: System Configuration Special Registers
S3C2500B SYSTEM CONFIGURATION 4.9 SYSTEM CONFIGURATION SPECIAL REGISTERS The System Configuration reigisters are as follows Table 4-5. System Configuration Registers Name Address Description Reset Value SYSCFG 0xF0000000 System configuration register – PDCODE 0xF0000004 Product code and revision number register 0x250000A0...
Page 228: System Configuration Register
SYSTEM CONFIGURATION S3C2500B 4.9.1 SYSTEM CONFIGURATION REGISTER (SYSCFG) You can control the system bus arbitration method, PLL operation, system clock output enable/disable function, external memory address remap function and Little/Big information read function by SYSCFG. Register Address Description Reset Value...
Page 229 SDRAM1 bank1 : 0x40000000 MISALIGN Misalign Exception Enable S3C2500B asserts the data abort exception in case of CPU misaligned accesses. But there is a limitation to that you should set off Instruction/Data cache when you want misaligned access aborts. HCLKO_DIS HCLKO output disable If this bit is set to “1”, HCLKO output is activated only when sdram...
Page 230: Product Code And Revision Number Register
SYSTEM CONFIGURATION S3C2500B 4.9.2 PRODUCT CODE AND REVISION NUMBER REGISTER (PDCODE) Register Address Description Reset Value PDCODE 0xF0000004 Product code and revision number register 0x250000B0 PDCODE Description Initial State [31-16] Product code 0x2500 Reserved [15:8] Reserved MajRev [7:4] Major revision number...
Page 231: Clock Control Register
S3C2500B SYSTEM CONFIGURATION 4.9.3 CLOCK CONTROL REGISTER (CLKCON) There is a clock control register(CLKCON) in system configuration. For the purpose of power save, Clock control register(CLKCON) can be programmed at low frequency and the slower clock than the system clock can be made by clock dividing value .
Page 232: Peripheral Clock Disable Register
SYSTEM CONFIGURATION S3C2500B 4.9.4 PERIPHERAL CLOCK DISABLE REGISTER (PCLKDIS) There is a peripheral clock disable register in system configuration. You can set this register with the specific value for the purpose of power save. If you set PCLKDIS[0] to “1”, the clock for GDMA channel 0 is disabled.
Page 233: Clock Status Register
SYSTEM CONFIGURATION 4.9.5 CLOCK STATUS REGISTER (CLKST) The operating frequency of the S3C2500B can be obtained by reading the CLKST register. The CPU Freq field in CLKST[11:0] decodes the CPU_FREQ[2:0] settings and the BUS Freq in CLKST[23:12] decodes the BUS_FREQ[2:0] settings. There are 3 clock modes in the S3C2500B - fast mode, sync mode and async mode. In async mode, there is no misinformation about the frequency.
Page 234: Core Pll Control Register
SYSTEM CONFIGURATION S3C2500B 4.9.7 CORE PLL CONTROL REGISTER (CPLLCON) If you want to use this register, you should set CPLLREN in SYSCFG[31] to “1”. This register doesn’t work with CPLLREN set to “0”. Register Address Description Reset Value CPLLCON 0xF000001C...
Page 235: System Bus Pll Control Register
S3C2500B SYSTEM CONFIGURATION 4.9.8 SYSTEM BUS PLL CONTROL REGISTER (SPLLCON) If you want to use this register, you should set SPLLREN in SYSCFG[30] to “1”. This register doesn’t work with SPLLREN set to “0”. Register Address Description Reset Value SPLLCON...
Page 236: Usb Pll Control Register
SYSTEM CONFIGURATION S3C2500B 4.9.9 USB PLL CONTROL REGISTER (UPLLCON) If you want to use this register, you should set UPLLREN in SYSCFG[29] to “1”. This register doesn’t work with UPLLREN set to “0”. Register Address Description Reset Value UPLLCON 0xF0000024...
Page 237: Memory Controller
DMA controller or CPU generates an address that corresponds to a SDRAM bank, the SDRAM controller generates the required SDRAM access signals. • To provide the required signals for bus traffic between the S3C2500B and ROM/SRAM and the external I/O banks. • •...
Page 238: Features
By generating an external bus request, an external device can access the S3C2500B's external memory interface pins. In addition, the S3C2500B can access slow external devices by using a WAIT signal. The WAIT signal, which is generated by the external device, extends the duration of the CPU’s memory...
Page 239: Memory Map
S3C2500B MEMORY CONTROLLER 5.3 MEMORY MAP After a power-on or system reset, all bank address pointer registers are initialized to their default values. And the base address of all banks are fixed. The initial system memory map following system start-up is shown in Figure 5-1.
Page 240 MEMORY CONTROLLER S3C2500B 0xFFFFFFFF Internal Register 0xF0000000 Reserved 0x88000000 Bank 1 0x80000000 Reserved 0x48000000 Bank 0 0x40000000 Reserved 0x08000000 EXT I/O Bank 7 0x07000000 EXT I/O Bank 6 0x06000000 EXT I/O Bank 5 0x05000000 EXT I/O Bank 4 0x04000000 EXT I/O Bank 3...
Page 241: Bus Interface Signals
MEMORY CONTROLLER 5.4 BUS INTERFACE SIGNALS The bus interface signals transfer information between the S3C2500B and external memory device. These divide into address and data which used commonly, SDRAM interface signals for SDRAM and memory device interface for ROM/SRAM, etc.
Page 242 MEMORY CONTROLLER S3C2500B ADDR[23:0] Address & Data DATA[31:0] B0SIZE[1:0] Adjust with pin selection nRCS[7:0] ROM & SRAM nEWAIT/nREADY Interface signals XBMACK External device XBMREQ interface signals S3C2500B nSDWE/nWE16 ROM, SRAM, Flash nWBE/nBE/DQM[3:0] and SDRAM common signals HCLKO nSDCS[1:0] SDRAM Interface...
Page 243: Endian Modes
MEMORY CONTROLLER 5.5 ENDIAN MODES S3C2500B supports both little-endian and big-endian for external memory or I/O devices by setting the pin BIG. Below tables(5-3 through 5-14) are show the program/data path between the CPU register and the external memory using little-/big-endian and word/half-word/byte access.
Page 244 MEMORY CONTROLLER S3C2500B Table 5-5 and 5-6. Using big-endian and half-word access, Program/Data path between register and external memory. WA=Address whose LSB is 0, 4, 8, C, EA=External Address HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E BA=Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F X=Don't care.
Page 245 S3C2500B MEMORY CONTROLLER Table 5-7 and 5-8. Using big-endian and byte access, Program/Data path between register and external memory. WA=Address whose LSB is 0, 4, 8, C, EA=External Address HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E BA=Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F X=Don't care.
Page 246 MEMORY CONTROLLER S3C2500B Table 5-9 and 5-10. Using little-endian and word access, Program/Data path between register and external memory. WA=Address whose LSB is 0, 4, 8, C, EA=External Address HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E...
Page 247 S3C2500B MEMORY CONTROLLER Table 5-11 and 5-12. Using little-endian and half-word access, Program/Data path between register and external memory. WA=Address whose LSB is 0, 4, 8, C, EA=External Address HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E BA=Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F X=Don't care.
Page 248 MEMORY CONTROLLER S3C2500B Table 5-13 and 5-14. Using little-endian and byte access, Program/Data path between register and external memory. WA=Address whose LSB is 0, 4, 8, C, EA=External Address HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E BA=Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F X=Don't care.
Page 249: Ext I/O Bank Controller
S3C2500B MEMORY CONTROLLER 5.6 EXT I/O BANK CONTROLLER Ext I/O Bank controller can be interfaceing ROM, SRAM, flash memory, etc, except SDRAM. It also supports muxed bus memory device which shares address bus and data bus. Ext I/O bank controller has three kind of the register for eight banks and then it can be controlled by various timing control options.
Page 250: External Device Connection
MEMORY CONTROLLER S3C2500B 5.6.2 EXTERNAL DEVICE CONNECTION Figure 5-3. illustrates a simple connection between 8-bit ROM/Flash and S3C2500B. ADDR[23:0] ADDR DATA[7:0] DATA 8-bit ROM/ nRCS[0] Flash nWBE[0] S3C2500B Figure 5-3. 8-bit ROM, SRAM and Flash Basic Connection 5-14...
Page 251 S3C2500B MEMORY CONTROLLER Figure 5-4. illustrates a example connection between two of 8-bit ROM/Flash and S3C2500B for the consisting of 16-bit ROM/SRAM/Flash. ADDR[23:0] ADDR[23:0] DATA[7:0] DATA[7:0] nRCS[0] 8-bit ROM/Flash nWBE[0] S3C2500B ADDR[23:0] DATA[15:8] DATA[7:0] 8-bit ROM/Flash nWBE[1] Figure 5-4. 8-bit ROM, SRAM and Flash Basic Connection (8-bit Memory x 2)
Page 252 MEMORY CONTROLLER S3C2500B Figure 5-5. illustrates a connection between 16-bit ROM/SRAM and S3C2500B. ADDR[23:0] ADDR DATA[15:0] DATA nSDWE/nWE16 16-bit SRAM nRCS nBE[1] S3C2500B Upper byte nBE[0] Lower byte Figure 5-5. 16-bit SRAM Basic Connection 5-16...
Page 253 S3C2500B MEMORY CONTROLLER Figure 5-6. illustrates a connection between 16-bit ROM/Flash and S3C2500B. ADDR[23:0] ADDR DATA[15:0] DATA nRCS 16-bit ROM/Flash nSDWE/nWE16 S3C2500B Figure 5-6. 16-bit ROM and Flash Basic Connection 5-17...
Page 254 MEMORY CONTROLLER S3C2500B Figure 5-7. illustrates a connection between 16-bit ROM and S3C2500B. ADDR[23:0] ADDR DATA[31:0] DATA[15:0] DATA 16-bit ROM nRCS nSDWE/nWE16 S3C2500B ADDR DATA[31:16] DATA 16-bit ROM Figure 5-7. 16-bit ROM Basic Connection 2 5-18...
Page 255 S3C2500B MEMORY CONTROLLER Figure 5-8. illustrates a connection between 16-bit SRAM and S3C2500B. ADDR[23:0] ADDR DATA[31:0] DATA[15:0] DATA 16-bit ROM nRCS nWBE[1] Upper byte nWBE[0] Lower byte S3C2500B ADDR DATA[31:16] DATA 16-bit ROM nWBE[3] Upper byte nWBE[2] Lower byte Figure 5-8. 16-bit SRAM Basic Connection 2...
Page 256 MEMORY CONTROLLER S3C2500B Figure 5-9. illustrates a connection between S3C2500B and muxed bus ROM & SRAM. ADDR[23]/ALE DATA[7:0] DATA[7:0] nRCS nWBE nWBE S3C2500B nREADY nREADY Figure 5-9. ROM & SRAM with Muxed Address & Data Bus Connection NOTE If the external I/O use nReady signal insteady of nWait, you must select nReady in WAITCON register of memory controller.
Page 257: Ext. I/O Bank Controller Special Register
S3C2500B MEMORY CONTROLLER 5.6.3 EXT. I/O BANK CONTROLLER SPECIAL REGISTER To control the external memory operations, the memory controller uses a dedicated set of special registers (see Table 5-15). By programming the values in the memory controller special registers, you can specify such things as •...
Page 258 The Ext I/O Bank controller has eight external I/O access control registers. These registers correspond to up to eight external I/O banks that are supported by S3C2500B. Table 5-16 describes eight registers that are used to control the timing of external I/O bank accesses.
Page 259 S3C2500B MEMORY CONTROLLER Table 5-16. Bank n Control (BnCON) Register Register Address Description Reset Value B0CON 0xF0010000 Bank 0 control register 0xC514E488 (B0SIZE=3) 0x8514E488 (B0SIZE=2) 0x4514E488 (B0SIZE=1) B1CON 0xF0010004 Bank 1 control register 0xC514E488 B2CON 0xF0010008 Bank 2 control register...
Page 260 MEMORY CONTROLLER S3C2500B 30 29 21 20 TACC TACS TCOS TCOH [3:0] Chip selection hold time on nOE: TCOH 0000 = 0 cycle 0001 = 1 cycle 0010 = 2 cycles 0011 = 3 cycles 0100 = 4 cycles 0101 = 5 cycles...
Page 261 S3C2500B MEMORY CONTROLLER NOTES 1. If WAITEN of WAITCON register is enable, memory controller can't finish access cycle until nEWAIT signal is high. If you use slow device, you can set WAITEN to '1' and control nEWAIT signal. The memory controller checks nEWAIT signal at the last cycle of TACC. If you set WAITEN to '0', the f nEWAIT signal is ignored.
Page 262 MEMORY CONTROLLER S3C2500B 30 29 26 25 21 20 [2-0] Muxed bus address cycle for bank 0: TMA0 001 = 1 cycle 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles...
Page 263 I/O devices are connected to nEWAIT, each WAIT signals of external I/O devices should be or.) nEWAIT is low active signal. When nEWAIT is a low, S3C2500B is waiting until nEWAIT is high again. nREADY in the WAITCON register is used when the external I/O device is ready for transferring data. When nREADY is low, S3C2500B transfers data.
Page 264 MEMORY CONTROLLER S3C2500B 21 20 Reserved [31:24] Reserved [23] TCOH disable for bank 7: COHDIS7 This forces TCOH to '0' for read to read, write to write, and write to read access in the bank 7 0 = disable 1 = enable...
Page 265: Timing Diagram
S3C2500B MEMORY CONTROLLER 5.6.4 TIMING DIAGRAM HCLKO tRCSd tRCSh tACC nRCS tnOEd tnOEh tADDRd tADDRh ADDR Addr tDATAh tDATAd DATA Data D ata Fetch TACC = 0x8 (8 cycles) TCOS = 0x0 (0 cycle) TCOH = 0x0 (0 cycle) TACS = 0x0 (0 cycle) Figure 5-14.
Page 266 MEMORY CONTROLLER S3C2500B HCLKO tRCSd tRCSh tACC nRCS tnSDWEh tnSDWEd nSDWE tADDRh tADDRd ADDR Addr tDATAd tDATAh DATA Data TACC = 0x8 (8 cycles) TCOS = 0x0 (0 cycle) TCOH = 0x0 (0 cycle) TACS = 0x0 (0 cycle) Figure 5-15. Write Timing Diagram 1...
Page 267 S3C2500B MEMORY CONTROLLER HCLKO tRCSh tRCSd tCOH tACC tACS nRCS tCOS tnOEh tADDRh tADDRd tnOEd ADDR Addr tDATAh tDATAd DATA Data Data Fetch TACC = 0x5 (5 cycles) TCOS = 0x1 (1 cycle) TCOH = 0x1 (1 cycle) TACS = 0x1 (1 cycle) Figure 5-16.
Page 268 MEMORY CONTROLLER S3C2500B HCLKO tRCSd tRCSh tACC tCOH nRCS tACS tCOS tnSDWEd tnSDWEh nSDWE tADDRd tADDRh ADDR Addr tDATAd tDATAh Data DATA TACC = 0x5 (5 cycles) TCOS = 0x1 (1 cycle) TCOH = 0x1 (1 cycle) TACS = 0x1 (1 cycle) Figure 5-17.
Page 269 S3C2500B MEMORY CONTROLLER Figure 5-18. Read after Write at the Same Bank (COHDIS = 1) 5-33...
Page 270 MEMORY CONTROLLER S3C2500B HCLKO tRCSd tRCSh tACC tCOH nRCS tCOS tnOEh tALEd tALEh tnOEd tDATAd tDATAh DATA Addr Data tADDRd tADDRh Data Fetch TACC = 0x4 (4 cycles) TCOS = 0x1 (1 cycle) TCOH = 0x1 (1 cycle) TMA = 0x2 (2 cycles) MBE = 1 (Enable) Figure 5-19.
Page 271 S3C2500B MEMORY CONTROLLER HCLKO tGCSd tGCSh tACC tCOH nRCS tCOS tnSDWEh nSDWE tALEd tnSDWEd tALEh tDATAd tDATAh Addr DATA Data tADDRd tADDRh Data Fetch TACC = 0x4 (4 cycles) TCOS = 0x1 (1 cycle) TCOH = 0x1 (1 cycle) TMA = 0x2 (2 cycles) MBE = 1 (Enable) Figure 5-20.
Page 272 MEMORY CONTROLLER S3C2500B HCLKO tRCSd tRCSh tACC nRCS tACS tCOS tnSDWEh nSDWE tnSDWEd ADDR Addr tDATAd tDATAh tADDRd tADDRh DATA Data nEWAIT /nReady tnWAITd tnWAITh TACC = 0x5 (5 cycles) TCOS = 0x1 (1 cycle) TCOH = 0x0 (0 cycle)
Page 273 S3C2500B MEMORY CONTROLLER HCLKO tRCSd tRCSh tACC nRCS tACS tCOS tnSDWEh nSDWE tnSDWEd ADDR Addr tDATAh tDATAd tADDRd tADDRh DATA Data nEWAIT /nReady tnWAITd tnWAITh TACC = 0x5 (5 cycles) TCOS = 0x1 (1 cycle) TCOH = 0x0 (0 cycle)
Page 274: Sdram Controller
MEMORY CONTROLLER S3C2500B 5.7 SDRAM CONTROLLER 5.7.1 FEATURES The SDRAM controller provides the following features: • Provides merging write buffer to improve system performance. • Supports for 16M-bit, 64M-bit, 128M-bit and 256M-bit SDRAM devices with two or four leaves. •...
Page 275: Sdram Size And Configuration
S3C2500B MEMORY CONTROLLER 5.7.2 SDRAM SIZE AND CONFIGURATION The SDRAM controller supports a SDRAM memory ranging from 2 to 256M-byte. Table 5-19. Illustrates the supported SDRAM configurations when external bus width is 32-bits. Table 5-20. Illustrates the supported SDRAM configurations when external bus width is 16 bits.
Page 276 MEMORY CONTROLLER S3C2500B Table 5-19. Supported SDRAM Configuration of 32-bit External Bus SDRAM SDRAM # Banks Address Size Leaf Select Total Technology Arrangement Memory Size ADDR[14] ADDR[13] (Byte) 2M × 8 16M-bit – HADDR[21] 16 M 1M × 16 –...
Page 277 S3C2500B MEMORY CONTROLLER Table 5-20. Supported SDRAM Configuration of 16-bit External Bus SDRAM SDRAM # Banks Address Size Leaf Select Total Technology Arrangement Memory Size ADDR[14] ADDR[13] (Byte) 2M × 8 16M-bit – HADDR[20] 1M × 16 – HADDR[20] 8M × 8...
Page 278: Address Mapping
MEMORY CONTROLLER S3C2500B 5.7.3 ADDRESS MAPPING Table 5-21. Illustrates the AHB address bus to the SDRAM address ADDR[14:0] mapping for various memory devices when external bus width is 32-bits. Table 5-22. Illustrates the AHB address bus to the SDRAM address ADDR[14:0] mapping for various memory devices when external bus width is 16-bits.
Page 279 S3C2500B MEMORY CONTROLLER Table 5-22. SDRAM address mapping of 16-bit external bus SDRAM Column Address (AddrOut[14:0]) Technology 2M × 8 16M-bit 1M × 16 8M × 8 64M-bit 4M × 16 16M × 8 128M-bit 8M × 16 32M × 8 256M-bit 16M ×...
Page 280: Sdram Commands
MEMORY CONTROLLER S3C2500B 5.7.4 SDRAM COMMANDS The SDRAM controller issues specific commands to the SDRAM devices by encoding the nSDCS, nSDRAS, nSDCAS and nSDWE outputs. Table 5-23. Lists all of the SDRAM commands understood by SDRAM devices. The controller supports a subset of these commands.
Page 281: External Data Bus Width
S3C2500B MEMORY CONTROLLER 5.7.5 EXTERNAL DATA BUS WIDTH The SDRAM controller supports not only 32-bit data bus, but also 16-bit data bus. External data bus width can be selected by the XW field of CFGREG. 5.7.6 MERGING WRITE BUFFER A merging write buffer compacts the writes of all widths into quad-word, which can be efficiently transferred to the SDRAM.
Page 282: Basic Operation
MEMORY CONTROLLER S3C2500B 5.7.8 BASIC OPERATION SDRAM initialization sequence On power-on reset, software must initialize the SDRAM controller and each of the SDRAM connected to the controller. Refer to the SDRAM data sheet for more detailed information on the start up procedure for the SDRAM used.
Page 283: Sdram Special Registers
S3C2500B MEMORY CONTROLLER 5.7.9 SDRAM SPECIAL REGISTERS The address and reset value of the special registers in the SDRAM controller summarized in Table 5-24. Table 5-24. SDRAM Special Registers Name Address Description Reset value CFGREG 0xF0020000 Configuration register 0x00099F0C CMDREG...
Page 284 MEMORY CONTROLLER S3C2500B Table 5-25. SDRAM Configuration Register (Continue) Reg0 Description Default value External data bus Width 0 = external bus width is 32-bit. 1 = external bus width is 16-bit. Auto Pre-charge control for SDRAM accesses 0 = Auto pre-charge...
Page 285 S3C2500B MEMORY CONTROLLER 20 19 12 11 10 9 8 7 6 RESERVED [0] eXternal data bus Width : XW 0 = external bus width is 32 bit ,1 = external bus width is 16 bit [1] Auto Pre-charge control for SDRAM accesses: AP...
Page 286 MEMORY CONTROLLER S3C2500B 5.7.9.2 Command Register The configuration register 1 is 32-bit read/write (some bits are read only) register. The SDRAM initialization command, write buffer operation can be controlled by this register. Table 5-26. SDRAM Command Register Registers Address Description...
Page 287 S3C2500B MEMORY CONTROLLER RESERVED [1:0] Control bits for SDRAM device initialization : 00 = Normal operation 01 = Automatically issue a PALL to the SDRAM 10 = Automatically issue a MRS to the SDRAM 11 = reserved [2] Write buffer enable:...
Page 288 MEMORY CONTROLLER S3C2500B 5.7.9.3 Refresh Timer Register The Refresh timer register is 32-bit read/write (some bits are read only) register. This register sets the SDRAM refresh cycle. The refresh timer register is programmed with the number of system bus clock that should be counted between SDRAM refresh cycles.
Page 289 S3C2500B MEMORY CONTROLLER 5.7.9.4 Write Buffer Time-out Register The write buffer time-out register works with the merging write buffer (if write buffer is enabled). This 16-bit read/write field of register sets the cycles for a forced flush of the write buffer.
Page 290: Sdram Controller Timing
MEMORY CONTROLLER S3C2500B 5.7.10 SDRAM CONTROLLER TIMING HCLKO tRCD tCSd nSDCS tCSh tRASd nSDRAS tCASd tRASh nSDCAS tCASh tADDRh tADDRd Row Addr. Col. Addr. ADDR tRDd DATA Data Latency tRDh nSDWE Latency tDQMd DQM/ nWBE tDQMh Row Active Read Figure 5-27. Single Read Operation (CAS Latency=2)
Page 291 S3C2500B MEMORY CONTROLLER HCLKO tRCD tCSd nSDCS tCSh tRASd nSDRAS tCASd tRASh nSDCAS tCASh tADDRh tADDRd ADDR Row Addr. Col. Addr. tRDd DATA Data CAS Latency tRDh nSDWE Latency tDQMd DQM/ nWBE tDQMh Row Active Read Figure 5-28. Single Read Operation (CAS Latency=3)
Page 292 MEMORY CONTROLLER S3C2500B HCLKO tRCD tCSd nSDCS tCSh tRASd nSDRAS tCASd tRASh nSDCAS tCASh tADDRh tADDRd Col. Addr. Row Addr. ADDR tWDd Data DATA tWDh tWEd nSDWE tWEh tDQMd DQM / nWBE tDQMh Row Active Write Figure 5-29. Single Write Operation...
Page 293 S3C2500B MEMORY CONTROLLER HCLKO tRCD tCSd nSDCS tCSh tRASd nSDRAS tCASd tRASh nSDCAS tADDRh tCASh tADDRd Row Addr. Col. Addr. ADDR tRDd Data Data Data Data DATA CAS Latency tRDh nSDWE DQM Latency tDQMd DQM/ nWBE tDQMh Row Active Write Figure 5-30.
Page 294 MEMORY CONTROLLER S3C2500B HCLKO tRCD tCSd nSDCS tCSh tRASd nSDRAS tCASd tRASh nSDCAS tADDRh tCASh tADDRd Row Addr. Col. Addr. ADDR tRDd Data Data Data Data DATA CAS Latency tRDh nSDWE DQM Latency tDQMd DQM/ nWBE tDQMh Row Active Write Figure 5-31.
Page 295 S3C2500B MEMORY CONTROLLER HCLKO tRCD tCSd nSDCS tCSh tRASd nSDRAS tCASd tRASh nSDCAS tADDRh tCASh tADDRd ADDR Row Addr. Col. Addr. tWDd Data Data Data Data DATA tWEd tWDh nSDWE tWEh tDQMd DQM/ nWBE tDQMh Row Active Write Figure 5-32. Burst Write Operation...
Page 296 MEMORY CONTROLLER S3C2500B NOTES 5-60...
Page 297: Chapter 6 I 2 C Controller
6.2 FEATURES • Supports only single master mode. • Supports 8-bit, bi-directional, serial data transfers. • Supports 7-bit addressing. Figure 6-1 shows a block diagram of the S3C2500B I C controller Data Shift buffer register (IICBUF) Control Serial Serial Clock...
Page 298: Functional Description
C CONTROLLER S3C2500B 6.3 FUNCTIONAL DESCRIPTION The S3C2500B I C controller is the master of the serial I C. Using a prescaler register, the user can program the serial clock frequency that is supplied to the I C controller. The serial clock frequency is calculated as follows: / (16 ×...
Page 299: I 2 C Concepts
S3C2500B C CONTROLLER 6.4 I C CONCEPTS 6.4.1 BASIC OPERATION The I C has two wires, a serial data line (SDL) and a serial clock line (SCL), to carry information between the ICs connected to the bus. Each IC is recognized by a unique address and can operate as either a transmitter or receiver, depending on the function of the specific ICs.
Page 300: General Characteristics
C CONTROLLER S3C2500B Acknowledge Acknowledge from from receiver transmitter SDA by Transmitter SDA by Receiver SCL from Master Stop Start Data Address Condition Condition Figure 6-3. Master Receiver and Slave Transmitter Even in this case, the master IC generates the timing and terminates the transfer.
Page 301: Data Validity
S3C2500B C CONTROLLER 6.4.4 DATA VALIDITY The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can only change when clock signal on the SCL line is low.
Page 302: Data Trsansfer Operations
C CONTROLLER S3C2500B 6.4.6 DATA TRSANSFER OPERATIONS 6.4.6.1 Data Byte Format Every data byte that is put on the SDA line must be 8 bits long. The number of bytes that can be transmitted per transfer is unlimited. Each byte must be followed by an acknowledge bit. Data is transferred MSB-first.
Page 303 S3C2500B C CONTROLLER 6.4.6.3 Data Transfer Format Data transfers uses the format shown in Figure 6-5. After the start condition has been generated, a 7-bit slave address is sent. The eighth bit is a data direction bit (R/W). A "0" direction bit indicates a transmission (Write) and a "1"...
Page 304 C CONTROLLER S3C2500B 6.4.6.4 I C Addressing The addressing procedure for the I C is such that the first byte after the start condition determines which slave the master will select. Usually, this first byte immediately follows the start procedure.
Page 305: I 2 C Special Registers
S3C2500B C CONTROLLER 6.5 I C SPECIAL REGISTERS The I C controller has three special registers: a control status register (IICCON), a prescaler register (IICPS), and a shift buffer register (IICBUF). 6.5.1 CONTROL STATUS REGISTER (IICCON) The control status register for the I C, IICCON, is described in Table 6-2.
Page 306 C CONTROLLER S3C2500B 6 5 4 3 2 1 Reserved [0] Buffer Flag (BF) 0 = Automatically cleared when the IICBUF register is written or read. To manually clear the BF, write 0. 1 = Automatically set when the buffer is empty in transmit mode or when the buffer is full in receive mode.
Page 307: Shift Buffer Register
S3C2500B C CONTROLLER 6.5.2 SHIFT BUFFER REGISTER (IICBUF) The shift buffer register for the I C described in Table 6-4. Table 6-3. IICBUF Register Register Address Description Rest Value IICBUF 0xF00F0004 Shift buffer register Undefined Table 6-4. IICBUF Register Description...
Page 308: Prescaler Counter Register
C CONTROLLER S3C2500B 6.5.4 PRESCALER COUNTER REGISTER (IICCNT) The prescaler counter register for the I C is described in Table 6-8. Table 6-7. IICCNT Register Register Address Description Rest Value IICCNT 0xF00F000C Prescaler counter register 0x00000000 Table 6-8. IICCNT Register Description...
Page 309 S3C2500B C CONTROLLER IIC Setup (Reset, IICPS Setup) IICCON = Start | BF IICBUF = IIC Slave Address | 0 x 0 IICBUF = IIC Upper Address IICBUF = IIC Lower Address IICBUF = One Byte Data All Data Sent? IICCON = Stop Figure 6-7.
Page 310 C CONTROLLER S3C2500B IIC Setup (Reset, IICPS Setup) IICCON = Start | BF IICBUF = IIC Slave Address | 0 x 0 IICBUF = IIC Upper Address IICBUF = IIC Lower Address IICCON = Repeated Start | ACK IICCON = Start | ACK...
Page 311: Chapter 7 Ethernet Controller
ETHERNET CONTROLLER 7.1 OVERVIEW The S3C2500B has two Ethernet controllers that operate at either 100M-bit or 10M-bit per second in half-duplex or full-duplex mode. In half-duplex mode, the IEEE 802.3 carrier sense multiple access with collision detection (CSMA/CD) protocol is supported. In full-duplex mode, the IEEE 802.3 MAC control layer is also supported, including the pause operation for flow control.
Page 312: Features
ETHERNET CONTROLLER S3C2500B 7.2 FEATURES The most important features and benefits of each Ethernet controller are as follows: • Cost-effective connection to an external RIC(Repeater Interface Controller)/Ethernet backbone • Buffered DMA (BDMA) engine with burst mode • BDMA Tx/Rx Buffers (BTxBUFF and BRxBUFF: 256 bytes/256 bytes) •...
Page 313: Mac Function Blocks
S3C2500B ETHERNET CONTROLLER 7.3 MAC FUNCTION BLOCKS The major function blocks of each Ethernet of MAC layer are described in Table 7-1 and Figure 7-1. Table 7-1. MAC Function Block Descriptions Function Block Description Media Independent The interface between the physical layer and the transmit/receiver blocks.
Page 314: Physical Layer Entity (Phy)
ETHERNET CONTROLLER S3C2500B 7.3.2 PHYSICAL LAYER ENTITY (PHY) The physical layer entity, or PHY, performs all of the decoding/encoding on incoming and outgoing data. The manner of decoding and encoding (Manchester for 10BASE-T, 4B/5B for 100BASE-X, or 8B/6T for 100BASE-T4) does not affect the MII.
Page 315 S3C2500B ETHERNET CONTROLLER 7.3.4.5 Threshold Logic and Counters The transmission state machine uses a counter and logic to control the threshold of when the transmission can begin. Before transmitting the MAC waits until eight bytes or a complete frame has been placed in the MTxFIFO.
Page 316: The Mac Receiver Block
ETHERNET CONTROLLER S3C2500B 7.3.5 THE MAC RECEIVER BLOCK It complies with the IEEE802.3 standard for carrier sense multiple access with collision detection (CSMA/CD) protocol. After it receives a frame, the receiver block checks for a number of error conditions: CRC errors, alignment errors, and length errors.
Page 317: Flow Control Block
S3C2500B ETHERNET CONTROLLER 7.3.6 FLOW CONTROL BLOCK Flow control is done using the MAC control frame. The receiver sends control frames to the transmitter and the transmitter pauses its operation during the time interval specified in the control frames. The flow control block provides the following functions: •...
Page 318 ETHERNET CONTROLLER S3C2500B 7.3.7.2 Control and Status This block controls the read/write operations of the bus master across the AMBA. The control logic supports the following operations: — Fixed 4-word burst size control between Tx and Rx. — Transmit threshold control (based on 1/8 of transmit buffer size) to match transmission latency to system bus latency.
Page 319 S3C2500B ETHERNET CONTROLLER 7.3.7.3 Buffer Descriptor The ownership bit in the buffer descriptor controls the owner of the descriptor. When the ownership bit is '1', the BDMA controller owns the descriptor. When the bit is '0', the CPU owns the descriptor. The owner of the descriptor always owns the associated data frame.
Page 320 ETHERNET CONTROLLER S3C2500B 18 17 Buffer Pointer TxStatus TxWidget TxLength [31:0] Buffer pointer Address of the data be transmitted. [31] Ownership bit (O) 0 = CPU 1 = BDMA [30:18] TxStatus Writing in this field don't have any mean. [30] Reserved [29] Paused Transmission of frame was paused due to the reception of a Pause control frame.
Page 321 S3C2500B ETHERNET CONTROLLER 29 28 27 26 Buffer Pointer B S E D Status RxLength [31:0] Buffer pointer Address of the frame data be saved. [31] Ownership bit (O) 0 = CPU 1 = BDMA [30] Skip BD (B) Set this bit to skip the current buffer descriptor when the ownership bit is cleared.
Page 322 ETHERNET CONTROLLER S3C2500B Buffer Descriptor Start Address Register buffer pointer #1 BRXBDCNT+0 status length buffer #1 BRxBS of BDMARXLEN not used buffer pointer #2 buffer #2 BRXBDCNT+1 status length BRxBS of BDMARXLEN not used buffer #N BRxBS of BDMARXLEN not used...
Page 323: Ethernet Controller Special Registers
S3C2500B ETHERNET CONTROLLER 7.4 ETHERNET CONTROLLER SPECIAL REGISTERS There are two Ethernet controllers in S3C2500B. They are same each other except the base addresses for internal registers. Table 7-2. ETHERNET 0 Special Registers Registers Address Description Reset Value BDMATXCONA 0xF00A0000...
Page 324 ETHERNET CONTROLLER S3C2500B Table 7-3. ETHERNET 1 Special Registers Registers Address Description Reset Value BDMATXCONB 0xF00C0000 Buffered DMA transmit control register 0x00000000 BDMARXCONB 0xF00C0004 Buffered DMA receive control register 0x00000000 BDMATXDPTRB 0xF00C0008 Transmit buffer descriptor start address 0x00000000 BDMARXDPTRB 0xF00C000C...
Page 325: Bdma Relative Special Register
S3C2500B ETHERNET CONTROLLER 7.4.1 BDMA RELATIVE SPECIAL REGISTER 7.4.1.1 Buffered DMA Transmit Control Register Table 7-4. BDMATXCON Register Registers Address Description Reset Value BDMATXCONA 0xF00A0000 Buffered DMA transmit control register 0x00000000 BDMATXCONB 0xF00C0000 Buffered DMA transmit control register 0x00000000 Table 7-5. BDMA Transmit Control Register Description...
Page 326 ETHERNET CONTROLLER S3C2500B 7.4.1.2 Buffered DMA Receive Control Register Table 7-6. BDMA RXCON Register Register Address Description Rest Value BDMARXCONA 0xF00A0004 Buffered DMA receive control register 0x00000000 BDMARXCONB 0xF00C0004 Buffered DMA receive control register 0x00000000 Table 7-7. BDMA Receive Control Register Description...
Page 327 S3C2500B ETHERNET CONTROLLER 7.4.1.3 BDMA Transmit Buffer Descriptor Start Address Register Table 7-8. BDMATXDPTR Register Registers Address Description Reset Value BDMATXDPTRA 0xF00A0008 BDMA Tx buffer descriptor base register 0x00000000 BDMATXDPTRB 0xF00C0008 BDMA Tx buffer descriptor base register 0x00000000 Table 7-9. BDMA Transmit Buffer descriptor Start Address Register Description...
Page 328 ETHERNET CONTROLLER S3C2500B 7.4.1.5 BDMA Transmit Buffer Descriptor Counter Table 7-12. BTXBDCNT Register Registers Address Description Reset Value BTXBDCNTA 0xF00A0010 BDMA Tx buffer descriptor counter of Current 0x00000000 Pointer BTXBDCNTB 0xF00C0010 BDMA Tx buffer descriptor counter of Current 0x00000000 Pointer Table 7-13.
Page 329 S3C2500B ETHERNET CONTROLLER 7.4.1.7 BDMA/MAC Transmit Interrupt Enable Register Table 7-16. BMTXINTEN Register Registers Address Description Reset Value BMTXINTENA 0xF00A0018 BDMA/MAC Tx Interrupt Enable 0x00000000 BMTXINTENB 0xF00C0018 BDMA/MAC Tx Interrupt Enable 0x00000000 Table 7-17. BDMA/MAC Transmit Interrupt Enable Register Description...
Page 330 ETHERNET CONTROLLER S3C2500B 7.4.1.8 BDMA/MAC Transmit Interrupt Status Register Table 7-18. BMTXSTAT Register Registers Address Description Reset Value BMTXSTATA 0xF00A0020 BDMA/MAC Tx Interrupt Status Register 0x00000000 BMTXSTATB 0xF00C0020 BDMA/MAC Tx Interrupt Status Register 0x00000000 Table 7-19. BDMA/MAC Transmit Interrupt Status Register Description...
Page 331 S3C2500B ETHERNET CONTROLLER 7.4.1.9 BDMA/MAC Receive Interrupt Enable Register Table 7-20. BMRXINTEN Register Registers Address Description Reset Value BMRXINTENA 0xF00A001C BDMA/MAC Rx Interrupt Enable Register 0x00000000 BMRXINTENB 0xF00C001C BDMA/MAC Rx Interrupt Enable Register 0x00000000 Table 7-21. BDMA/MAC Receive Interrupt Enable Register Description...
Page 332 ETHERNET CONTROLLER S3C2500B 7.4.1.10 BDMA/MAC Receive Interrupt Status Register Table 7-22. BMRXSTAT Register Registers Address Description Reset Value BMRXSTATA 0xF00A0024 BDMA/MAC Rx Interrupt Status register 0x00000000 BMRXSTATB 0xF00C0024 BDMA/MAC Rx Interrupt Status register 0x00000000 Table 7-23. BDMA/MAC Receive Interrupt Status Register Description...
Page 333 S3C2500B ETHERNET CONTROLLER 7.4.1.11 BDMA Receive Frame Size Register Table 7-24. BDMARXLEN Register Registers Address Description Reset Value BDMARXLENA 0xF00A0028 Receive frame size Undefined BDMARXLENB 0xF00C0028 Receive frame size Undefined Table 7-25. BDMA Receive Frame Size Register Description Bit Number...
Page 334: Mac Relative Special Register
ETHERNET CONTROLLER S3C2500B 7.4.2 MAC RELATIVE SPECIAL REGISTER 7.4.2.1 MAC Transmit Control Frame Status The transmit control frame status register, CFTXSTAT provides the status of a MAC control frame as it is sent to a remote station. This operation is controlled by the MSdPause bit in the transmit control register, MACTXCON.
Page 335 S3C2500B ETHERNET CONTROLLER 7.4.2.2 MAC Control Register The MAC control register provides global control and status information for the MAC. The MLINK10 bit is a status bit. All other bits are MAC control bits. MAC control register settings affect both transmission and reception.
Page 336 ETHERNET CONTROLLER S3C2500B 7.4.2.3 CAM Control Register The three acceptance bits (MStation, MGroup, and MBroad) in the CAM control register are used to override the address comparison mode by the compare enable bit(MCompEn). By setting the CAM control register, it is possible to accept frames with all types of destination addresses.
Page 337 S3C2500B ETHERNET CONTROLLER 7.4.2.4 MAC Transmit Control Register Table 7-32. MACTXCON Register Registers Address Description Reset Value MACTXCONA 0xF00B0008 Transmit control 0x00000000 MACTXCONB 0xF00D0008 Transmit control 0x00000000 Table 7-33. MAC Transmit Control Register Description Bit Number Bit Name Description Transmit enable (MTxEn) Set this bit to enable transmission.
Page 338 ETHERNET CONTROLLER S3C2500B 7.4.2.5 MAC Transmit Status Register A transmission status flag is set in the transmit status register, MACTXSTAT, whenever the corresponding event occurs. In addition, an interrupt is generated if the corresponding enable bit in the transmit control register is set.
Page 339 S3C2500B ETHERNET CONTROLLER 7.4.2.6 MAC Receive Control Register Table 7-36. MACRXCON Register Registers Offset Description Reset Value MACRXCONA 0xF00B0010 Receive control 0x00000000 MACRXCONB 0xF00D0010 Receive control 0x00000000 Table 7-37. MAC Receive Control Register Description Bit Number Bit Name Description Receive enable (MRxEn) Set this bit to '1' to enable MAC receive operation.
Page 340 ETHERNET CONTROLLER S3C2500B 7.4.2.7 MAC Receive Status Register A receive status flag is set in the MAC receive status register, MACRXSTAT, whenever the corresponding event occurs. When a status flag is set, it remains set until another packet arrives, or until software writes a ‘1’ to the flag to clear the status bit.
Page 341 S3C2500B ETHERNET CONTROLLER 7.4.2.8 MAC Station Management Data Register Table 7-40. STADATA Register Registers Address Description Reset Value STADATAA 0xF00B0018 Station management data 0x00000000 STADATAB 0xF00D0018 Station management data 0x00000000 Table 7-41. Station Management Register Description Bit Number Bit Name...
Page 342 ETHERNET CONTROLLER S3C2500B 7.4.2.9 MAC Station Management Data Control and Address Register The MAC controller provides support for reading and writing station management data to the PHY. Setting options in station management registers does not affect the controller. Some PHYs may not support the option to suppress preambles after the first operation.
Page 343 S3C2500B ETHERNET CONTROLLER 7.4.2.10 CAM Enable Register The CAMEN register indicates which CAM entries are valid, using a direct comparison mode. Up to 21 entries, numbered 0 through 20, may be active, depending on the CAM size. If the CAM is smaller than 21 entries, the higher bits are ignored.
Page 344 ETHERNET CONTROLLER S3C2500B 7.4.2.11 MAC Missed Error Count Register The value in the missed error count register, MISSCNT, indicates the number of frames that were discarded due to various type of errors. Together with status information on frames transmitted and received, the missed error count register and the two pause count registers provide the information required for station management.
Page 345 S3C2500B ETHERNET CONTROLLER 7.4.2.12 MAC Received Pause Count Register The received pause count register, PZCNT, stores the current value of the 16-bit received pause counter. Table 7-48. PZCNT Register Registers Address Description Reset Value PZCNTA 0XF00B0040 Pause count 0x00000000 PZCNTB...
Page 346 ETHERNET CONTROLLER S3C2500B 7.4.2.14 Content Addressable Memory (CAM) Register There are 21 CAM entries for the destination address and the pause control frame. For the destination address CAM value, one destination address consists of 6 bytes. Using the 32-word space (32 × 4 bytes), you can therefore maintain up to 21 separate destination addresses.
Page 347: Mac Frame Format
S3C2500B ETHERNET CONTROLLER 7.5 ETHERNET OPERATIONS 7.5.1 MAC FRAME FORMAT Table 7-2 lists the eight fields in a standard (IEEE 802.3/Ethernet frame). Table 7-53. MAC Frame Format Description Field Name Field Size Description Preamble 7-byte The bits in each preamble byte are 10101010, transmitted from left to right.
Page 348 ETHERNET CONTROLLER S3C2500B Packet (Encoded on the Medium) Data Frame (sent by user) Added by transmitter Added by Transmitter, Stripped by Data frame (delivered to user) Optionaly stripped Receiver by receiver Destination Source Length or Preamble LLC data Address Address...
Page 349 S3C2500B ETHERNET CONTROLLER 7.5.1.2 Destination Address Format Bit 0 of the destination address is an address type designation bit. It identifies the address as either an individual or a group address. Group addresses are sometimes called 'multicast' addresses and individual addresses are called 'unicast' addresses.
Page 350 ETHERNET CONTROLLER S3C2500B The back-off state machine The back-off state machine implements the back-off and retry algorithm of the 802.3 CSMA/CD. When a collision is detected, the main transmission state machine starts the back-off state machine′s counters and waits for the back-off time (including zero) to elapse. This time is a multiple of 512 bit times that elapse before the frame that caused the collision is re-transmitted.
Page 351 S3C2500B ETHERNET CONTROLLER The main transmission state machine The main transmission state machine implements the remaining MAC layer protocols. If there is data to be transferred, if the inter-frame gap is valid, and if the MII is ready (that is, if there are no collisions and no CRS in full-duplex mode), the transmitter block then transmits the preamble followed by the SFD.
Page 352 ETHERNET CONTROLLER S3C2500B Tx_clk Tx_en TxD [3:0] Figure 7-8. Timing for Transmission with Collision in Preamble 7.5.1.3.2. BDMA/MAC Interface Operation for Transmission The BDI transmit operation is a simple FIFO mechanism. The BDMA engine stores data to be transmitted, and the transmission state machine empties it when the MAC successfully acquires the net.
Page 353 S3C2500B ETHERNET CONTROLLER 7.5.1.4.1. Receive Frame Timing With/Without Error If, during frame reception, both Rx_DV and Rx_er are asserted, a CRC error is reported for the current packet. As each nibble of the destination address is received, the CAM block attempts to recognize it. After receiving the last destination address nibble, if the CAM block rejects the packet, the receive block asserts the Rx_toss signal, and discards any bytes not yet removed from the receive FIFO that came from the current packet.
Page 354 ETHERNET CONTROLLER S3C2500B 7.5.1.4.2 BDMA/MAC Interface Operation for Reception The BDI receive operation is a simple FIFO mechanism. The BDMA engine stores received data to MRxFIFO, and the BDMA RxBUFF controller empties it when the BDMA RxBUFF has enough space left.
Page 355: The Mii Station Manager
S3C2500B ETHERNET CONTROLLER 7.5.2 THE MII STATION MANAGER The MDIO (management data input/output) signal line is the transmission and reception path for control/status information for the station management entity, STA. The STA controls and reads the current operating status of the PHY layer.
Page 356: Full-Duplex Pause Operations
ETHERNET CONTROLLER S3C2500B 7.5.3 FULL-DUPLEX PAUSE OPERATIONS Flow control can be done by the use of control frames. The receive logic in the flow control block recognise a MAC control frame as follows: — The current specification for full-duplex flow control specifies a special destination address for the Pause operation frame.
Page 357 S3C2500B ETHERNET CONTROLLER 7.5.3.1 Transmit Pause Operation To enable a full-duplex Pause operation, the special broadcast address for MAC control frames must be programmed into the CAM, and the corresponding CAM enable bit set. The special broadcast address can be a CAM location.
Page 358: Error Signalling
ETHERNET CONTROLLER S3C2500B 7.5.4 ERROR SIGNALLING The error/abnormal operation flags asserted by the MAC are arranged into transmit and receive groups. These flag groups are located either in the transmit status register (MACTXSTAT) or the receive status register (MACRXSTAT). A missed frame error counter is included for system network management purposes.
Page 359 S3C2500B ETHERNET CONTROLLER 7.5.4.2 Reporting of Reception Errors When it detects a start of frame delimiter (SFD), the MAC starts putting data it has received from the MII into the MRxFIFO. It also checks for internal errors (MRxFIFO overruns) while reception is in progress.
Page 360: Timing Parameters For Mii Transactions
ETHERNET CONTROLLER S3C2500B 7.5.5 TIMING PARAMETERS FOR MII TRANSACTIONS The timing diagrams in this section conform to the guidelines described in the "Draft Supplement to ANSI/IEEE Std. 802.3, Section 22.3, Signal Characteristics." TX_CLK 28ns MIN 4.9ns MIN TXD[3:0] Output Valid TX_EN Figure 7-13.
Page 361: Chapter 8 Hdlc Controller
HDLC CONTROLLER HDLC CONTROLLER 8.1 OVERVIEW The S3C2500B has three high-level data link controllers (HDLCs) to support three-channel serial communica- tions. The HDLC module supports a CPU/data link interface that conforms to the synchronous data link control (SDLC) and high-level data link control (HDLC) standards. In addition, the following function blocks are integrated into the HDLC module: —...
Page 362: Features
HDLC CONTROLLER S3C2500B 8.2 FEATURES Important features of the S3C2500B HDLC block are as follows: • • Protocol features: — Flag detection and synchronization — Zero insertion and deletion — Idle detection and transmission — FCS encoding and detection (16-bit) —...
Page 363: Function Descriptions
S3C2500B HDLC CONTROLLER 8.3 FUNCTION DESCRIPTIONS Figure 8-1 shows the HDLC module's function blocks. These function blocks are described in detail in the following sections. Tx FIFO FCS Generator (8 Words) autoecho Address Flag/Abort/Idle Controlller Zero Encoder Generateor and Insertion...
Page 364: Hdlc Frame Format
HDLC CONTROLLER S3C2500B 8.3.1 HDLC FRAME FORMAT The HDLC transmits and receives data (address, control, information and CRC field) in a standard format called a frame. All frames start with an opening flag (beginning of flag, BOF, 7EH) and end with a closing flag (end of flag, EOF, 7EH).
Page 365 Not every frame, however, must actually contain information data. The word length of the I-field is eight bits in the S3C2500B HDLC module. And Its total length can be extended by 8 bits until terminated by the FCS field and the closing flag.
Page 366: Protocol Features
HDLC CONTROLLER S3C2500B 8.4 PROTOCOL FEATURES 8.4.1 INVALID FRAME A valid frame must have at least the A, C, and FCS fields between its opening and closing flags. Even if no-CRC mode is set, the frame size should not be less than 32 bits. There are three invalid frame conditions: —...
Page 367: Fifo Structure
S3C2500B HDLC CONTROLLER 8.4.5 FIFO STRUCTURE In both transmit and receive directions, 32-byte (8 word) deep FIFOs are provided for the intermediate storage of data between the serial interface and the CPU Interface. 8.4.6 TWO-CHANNEL DMA ENGINE The HDLC module has a two-channel DMA engine for Tx/Rx FIFOs. The DMA TX channel programming and the RX channel programming are described in the transmitter and receiver operation sections, respectively.
Page 368 HDLC CONTROLLER S3C2500B The example in the following Table assumes a 66MHz clock from MCLK2, a 24.576MHz clock from RxC, showing a time constant for a number of commonly used baud rates. Table 8-2. Baud Rate Example of HDLC R× × C = 24.576 MHz...
Page 369: Digital Phase-Locked Loop (Dpll)
S3C2500B HDLC CONTROLLER 8.4.8 DIGITAL PHASE-LOCKED LOOP (DPLL) The HDLC module contains a digital phase-locked loop (DPLL) function to recover clock information from a data stream with NRZI or FM encoding. The DPLL is driven by a clock that is normally 32 (NRZI) or 16 (FM) times the data rate.
Page 370 HDLC CONTROLLER S3C2500B In the NRZ/NRZI mode, the DPLL source clock must be 32 times the data rates. In this mode, the transmit and receive clock outputs of the DPLL are identical, and the clocks are phased so that the receiver samples the data in the middle of the bit cell.
Page 371: Hdlc Operational Description
S3C2500B HDLC CONTROLLER 8.5 HDLC OPERATIONAL DESCRIPTION The following sections describe the operation of the HDLC module. 8.5.1 HDLC INITIALIZATION A power-on or reset operation initializes the HDLC module and forces it into the reset state. After a reset, the CPU must write a minimum set of registers, as well as any options set, based on the features and operating modes required.
Page 372: Hdlc Data Encoding/Decoding
HDLC CONTROLLER S3C2500B 8.5.2 HDLC DATA ENCODING/DECODING Data encoding is utilized to allow the transmission of clock and data information over the same medium. This saves the need to transmit clocks and data over a separate medium as would normally be required for synchronous data.
Page 373: Hdlc Data Setup And Hold Timing With Clock
S3C2500B HDLC CONTROLLER 8.5.3 HDLC DATA SETUP AND HOLD TIMING WITH CLOCK You can see the timing of TxD and RxD in terms of TxC and RxC HDLC clock in Figure 8-6. Table 8-3. HDLC Data Setup and Hold Timing...
Page 374: Hdlc Transmitter Operation
HDLC CONTROLLER S3C2500B 8.5.4 HDLC TRANSMITTER OPERATION The HTxFIFO register cannot be pre-loaded when the transmitter is disabled. After the HDLC Tx is enabled, the flag or mark idle control bit (TxFLAG in HCON) is used to select either the mark idle state (inactive idle) or the flag 'time fill' (active idle) state.
Page 375 S3C2500B HDLC CONTROLLER 8.5.4.1 Transmitter Interrupt Mode The first byte of a frame (the address field) should be written into the Tx FIFO at the 'frame continue' address. Then, the transmission of the frame data starts automatically. The bytes of the frame continue to be written into the Tx FIFO as long as data is written to the 'frame continue' address.
Page 376: Hdlc Receiver Operation
HDLC CONTROLLER S3C2500B 8.5.5 HDLC RECEIVER OPERATION The HDLC receiver is provided with data and a pre-synchronized clock by means of the RXD and the internal DPLL clock, the TXC pin, or the RXC pin. The data is a continuous stream of binary bits. One of the characteristics of this bit stream is that a maximum of five consecutive 1s can occur unless an abort, flag, or idle condition occurs.
Page 377: Hardware Flow Control
S3C2500B HDLC CONTROLLER 8.5.5.2 Receiver DMA Mode To use DMA operation without CPU intervention, you have to make Rx buffer descriptor in advance. And set the DMA Rx buffer descriptor pointer(DMARxPTR) register to the address of the first buffer descriptor, set the Rx Buffer Descriptor Maximum Count (RxBDMAXCNT) register which shows the maximum buffer descriptor counts, and then DMA Rx channel should be enabled.
Page 378 HDLC CONTROLLER S3C2500B TxClock Data 5 - 12 cycles Figure 8-9. CTS Delayed on If nCTS remains still High for a while after nRTS enters Low to allow data transmission from HTxFIFO, the data transmission starts 5-12 cycles after nCTS is shifted to Low...
Page 379: Memory Data Structure
S3C2500B HDLC CONTROLLER 8.5.7 MEMORY DATA STRUCTURE The flow control to the HDLC controller uses two data structures to exchange control information and data. — Transmit buffer descriptor — Receive buffer descriptor Each Tx DMA buffer descriptor has the following elements.
Page 380: Data Buffer Descriptor
HDLC CONTROLLER S3C2500B 8.5.8 DATA BUFFER DESCRIPTOR Rx BDMA function is enabled by DRxEN bit(HCON[7]). When Rx BDMA is enabled, the BDMA fetches the Rx Buffer Data pointer and Owner bit of the next word. Then it checks the Ownership of the Buffer Descriptor. If the Owner bit is ‘1’, then BDMA owns the Buffer Descriptor, and BDMA waits until Rx.
Page 381: Buffer Descriptor
S3C2500B HDLC CONTROLLER 8.6 BUFFER DESCRIPTOR 8.6.1 TRANSMIT BUFFER DESCRIPTOR 26 25 Buffer Pointer Tx Control Bits Buffer Length [31:0] Buffer Data Pointer [15:0] Buffer Length Tx Control Bits [16] Preamble (P) 0 = No Preamble 1 = Preamble [17] TxNoCRC Mode (N)
Page 382: Receive Buffer Descriptor
HDLC CONTROLLER S3C2500B 8.6.2 RECEIVE BUFFER DESCRIPTOR Buffer Pointer Rx Control Bits Buffer Length [31:0] Buffer Data Pointer [15:0] Buffer Length Rx Status Bits These bits may be regarded as valid when L bit(in Rx status bit) is set [16] CD Lost (CD)
Page 383 S3C2500B HDLC CONTROLLER Rx Buffer Descriptor Start Address Buffer Data Pointer #1 Rx Bufsize Pointer Buffer Data #1 Register Status Buffer Length Value Unused Buffer Data Pointer #2 Rx Bufsize Status Buffer Length HRXBDMAXCNT = #N Buffer Data #2 Register...
Page 384: Hdlc Special Registers
HDLC CONTROLLER S3C2500B 8.7 HDLC SPECIAL REGISTERS The HDLC special registers are defined as read-only or write-only registers according to the direction of information flow. The addresses of these registers are shown in Table 8-4 and 8-5. The transmitter FIFO register can be accessed using two different addresses, the frame terminate address and the frame continue address.
Page 385 S3C2500B HDLC CONTROLLER Table 8-5. HDLC Channel B Special Registers Registers Address Description Reset Value HMODEB HDLC mode register 0×F0110000 0×00000000 HCONB 0×F0110004 HDLC control register 0×00000000 HSTATB 0×F0110008 HDLC status register 0×00000000 HINTENB 0×F011000C HDLC interrupt enable register 0×00000000...
Page 386 HDLC CONTROLLER S3C2500B Table 8-6. HDLC Channel C Special Registers Registers Address Description Reset Value HMODEC HDLC mode register 0×F0120000 0×00000000 HCONC 0×F0120004 HDLC control register 0×00000000 HSTATC 0×F0120008 HDLC status register 0×00000000 HINTENC 0×F012000C HDLC interrupt enable register 0×00000000...
Page 387: Hdlc Global Mode Register
S3C2500B HDLC CONTROLLER 8.7.1 HDLC GLOBAL MODE REGISTER Table 8-7. HMODEA, HMODEB, and HMODEC Register Registers Address Description Reset Value HMODEA HDLC Mode register 0×F0100000 0×00000000 HMODEB HDLC Mode register 0×F0110000 0×00000000 HMODEC 0×F0120000 HDLC Mode register 0×00000000 Table 8-8. HMODE Register Description...
Page 388 HDLC CONTROLLER S3C2500B Table 8-8. HMODE Register Description (Continued) Bit Name Description Number [14:12] Data formats (DF) When the DF bits are '000', data is transmitted and received in the NRZ data format. When DF is '001', the NRZI (zero complement) data format is selected.
Page 389 S3C2500B HDLC CONTROLLER 28 27 26 23 22 20 19 15 14 12 11 8 7 6 DPLL RxCLK TxCLK TxPL [0] Muilt-Frame in TxFIFO in DMA Operation (MFF) [15] RTRnRTS 0 = Single frame in TxFIFO 0 = Request to send...
Page 390: Hdlc Control Register
HDLC CONTROLLER S3C2500B 8.7.2 HDLC CONTROL REGISTER Table 8-9. HCONA , HCONB, and HCONC Register Registers Address Description Reset Value HCONA HDLC channel A control register 0x00000000 0×F0100004 HCONB HDLC channel B control register 0x00000000 0×F0110004 HCONC 0×F0120004 HDLC channel C control register 0x00000000 Table 8-10.
Page 391 S3C2500B HDLC CONTROLLER Table 8-10. HCON Register Description (Continued) Bit Name Description Number DMA Rx enable The DRxEN bit lets the HDLC Rx operate on a bus system in DMA mode. (DRxEN) When DMA Rx is enabled, an interrupt request caused by the RxFA status is inhibited, and the HDLC does not use the interrupt request to request a data transfer.
Page 392 HDLC CONTROLLER S3C2500B Table 8-10. HCON Register Description (Continued) Bit Name Description Number [13:12] Rx widget alignment These bits determine how many bytes are invalid in the first memory (RxWA) word of the frame to be received. The invalid bytes are inserted when the word is assembled in the HRXFIFO.
Page 393 S3C2500B HDLC CONTROLLER Table 8-10. HCON Register Description (Continued) Bit Name Description Number [23] Tx preamble (TxPRMB) When this bit is set to '1', the content of the HPRMB register is transmitted as many TxPL bit values in interrupt mode instead of mark idle or time fill mode.
Page 394 HDLC CONTROLLER S3C2500B 30 29 28 27 26 25 23 22 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 [0] Tx reset (TxRS) 0 = Normal 1 = TxFIFOmand Tx block are reset.
Page 395 S3C2500B HDLC CONTROLLER 30 29 28 27 26 25 18 17 16 10 9 8 7 6 23 22 20 19 15 14 13 12 11 [18] Tx single flat (TxSFLAG) 0 = Double flag mode (a closing & opening flags are used to separate frames)
Page 396: Hdlc Status Register
HDLC CONTROLLER S3C2500B 8.7.3 HDLC STATUS REGISTER (HSTAT) NOTE Reading the HDLC status register is a non-destructive process. The method used to clear a High-level status condition depends on the bit's function and operation mode(DMA or interrupt). For details, please see the description of each status register.
Page 397 S3C2500B HDLC CONTROLLER Table 8-12. HSTAT Register Description Bit Name Description Number [3:0] Rx remaining bytes (RxRB + 1) indicates how many data bytes are valid in a 1-word or 4- (RxRB) word boundary when the receiver has received a complete frame. In 1- word transfer mode, the RxRB value is either 0, 1, 2, or 3.
Page 398 HDLC CONTROLLER S3C2500B Table 8-12. HSTAT Register Description (Continued) Bit Name Description Number [11] Rx flag detected (RxFD) This bit is set to '1' when the last bit of the flag sequence is received. This bit generates an interrupt if enabled. You can clear this bit by writing a '1' to this bit.
Page 399 S3C2500B HDLC CONTROLLER Table 8-12. HSTAT Register Description (Continued) Bit Name Description Number [23] Rx internal error This bit is set to '1' when received frame will be detected error possibility (RxIERR) due to the receive clock is unstable. [24]...
Page 400 HDLC CONTROLLER S3C2500B 30 29 28 27 26 25 23 22 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 [3:0] Rx remaining bytes (RxRB) At 1-word boundary: At 4-word boundary: 0000 = Valid data byte is 1...
Page 401 S3C2500B HDLC CONTROLLER 30 29 28 27 26 25 23 22 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 [16] Rx abort (RxABT) 0= Normal operation 1 = Seven or more consecutive 1s have been received, in-frame condition.
Page 402: Hdlc Interrupt Enable Register
HDLC CONTROLLER S3C2500B 8.7.5 HDLC INTERRUPT ENABLE REGISTER (HINTEN) Table 8-13. HINTENA, HINTENB, and HINTENC Register Registers Address Description Reset Value HINTENA 0×F010000C HDLC Interrupt Enable Register 0X00000000 HINTENB 0×F011000C HDLC Interrupt Enable Register 0X00000000 HINTENC 0×F012000C HDLC Interrupt Enable Register 0X00000000 Table 8-14.
Page 403 S3C2500B HDLC CONTROLLER 30 29 28 27 26 25 18 17 16 10 9 8 7 6 23 22 20 19 15 14 13 12 11 [3:0] Reserved [4] Tx frame complete interrupt enable (TxFCIE) [5] Tx FIFO available to write interrupt enable (TxFAIE)
Page 404: Hdlc Tx Fifo
HDLC CONTROLLER S3C2500B 8.7.6 HDLC TX FIFO (HTXFIFO) The Tx FIFO consists of eight 32-bit registers that are used for buffer storage of data to be transmitted. Data is always transferred from a full register to an empty adjacent register. The Tx FIFO can be addressed at two different register addresses: the 'frame continue' address and the 'frame terminate' address.
Page 405: Hdlc Rx Fifo
S3C2500B HDLC CONTROLLER 8.7.7 HDLC RX FIFO (HRXFIFO) The Rx FIFO consists of eight 32-bit registers that are used for the buffer storage of the data received. Data bytes are always transferred from a full register to an adjacent empty register. Each register has pointer bits that indicate the frame status.
Page 406: Hdlc Brg Time Constant Registers
HDLC CONTROLLER S3C2500B 8.7.8 HDLC BRG TIME CONSTANT REGISTERS (HBRGTC) Table 8-15. HBRGTCA and HBRGTCB Register Registers Address Description Reset Value 0×F010001C HBRGTCA HDLC BRG Time Constant Register 0x00000000 0×F011001C HBRGTCB HDLC BRG Time Constant Register 0x00000000 0×F012001C HBRGTCC HDLC BRG Time Constant Register...
Page 407: Hdlc Preamble Constant Register
S3C2500B HDLC CONTROLLER 8.7.9 HDLC PREAMBLE CONSTANT REGISTER (HPRMB) The HPRMB register is used to meet the DPLL requirements for phase-locking. The preamble pattern is transmitted as many Tx preamble length bit values in HMODE[10:8] when the Tx preamble bit (TxPRMB) is '1', and then the Tx preamble bit is cleared automatically.
Page 408 HDLC CONTROLLER S3C2500B 8.7.10 HDLC STATION ADDRESS REGISTERS (HSADR0-3) AND HMASK REGISTER Each HDLC controller has five 32-bit registers for address recognition: four station address registers and one mask register. Generally, the HDLC controller reads the address of the frame from the receiver, to check it against the four station address values, and then masks the result with the user-defined HMASK register.
Page 409: Dma Tx Buffer Descriptor Pointer Register
S3C2500B HDLC CONTROLLER First byte Second byte Third byte Fourth byte Station address byte register and MASK register [31:24] First address byte [23:16] Second address byte [15:8] Third address byte [7:0] Fourth address byte Figure 8-22. HDLC Station Address and HMASK Register 8.7.11 DMA TX BUFFER DESCRIPTOR POINTER REGISTER...
Page 410: Dma Rx Buffer Descriptor Pointer Register
HDLC CONTROLLER S3C2500B 8.7.12 DMA RX BUFFER DESCRIPTOR POINTER REGISTER The DMA receive buffer descriptor pointer register contains the address of the Rx buffer data pointer on the data to be received. During a DMA operation, the buffer descriptor pointer is updated by the next buffer data pointer.
Page 411: Receive Buffer Size Register
S3C2500B HDLC CONTROLLER 8.7.14 RECEIVE BUFFER SIZE REGISTER The Rx buffer size register contains the 16-bit user-defined value. This user-defined count value determines the buffer size for one Buffer Descriptor. If incoming HDLC frame is longer than the Rx buffer size register value, the next buffer descriptor having the Rx buffer size value will be used.
Page 412: Transparent Control Register
HDLC CONTROLLER S3C2500B 8.7.16 TRANSPARENT CONTROL REGISTER The HDLC transparent register controls the transparent data flow. This is composed with Data sampling field and RTS control field. Table 8-24. Transparent Control Register Registers Address Description Reset Value TCONA 0xF010004C Transparent Control Register...
Page 413: Tx Buffer Descriptor Count Register
S3C2500B HDLC CONTROLLER 8.7.17 TX BUFFER DESCRIPTOR COUNT REGISTER Tx Buffer Descriptor count register which shows how many Tx buffer descriptor is used. Table 8-25. HTXBDCNTA, HTXBDCNTB, and HTXBDCNTC Register Registers Address Description Reset Value HTXBDCNTA 0×F01000C0 Tx buffer descriptor count register 0×XXXXX000...
Page 414: Tx Buffer Descriptor Maximum Count Register
HDLC CONTROLLER S3C2500B 8.7.19 TX BUFFER DESCRIPTOR MAXIMUM COUNT REGISTER Tx Buffer Descriptor maximum count register sets tx buffer descriptor maximum counts. For example, if you set the HTXBDMAXCNT register to "0xFFF", then you can use 1(2 ) buffer descriptor. If you set the HTXBDMAXCNT register to "0xFFE", "0xFFC", "0xFF8", "0xFF0", "0xFE0", then you can use 2(2...
Page 415: Chapter 9 Iom2 & Tsa Controller
IOM2 & TSA CONTROLLER 9.1 OVERVIEW The IOM2-bus is an industry standard serial bus for interconnecting telecommunication ICs. The S3C2500B includes the IOM2 controller to enable a modular interface to the terminal network such as an ISDN interface. 9.2 FEATURES •...
Page 416: Iom2 Bus
These are a 1x-Bit rate Clock (BCL), and two Serial Data Strobes that identify the location of the B channels (SDS1 and SDS2). The S3C2500B includes two optional signals, BCL and SDS1. SDS1 is called STRB in S3C2500B. In S3C2500B, the terminal mode operation is supported but line-card mode is not supported.
Page 417: B Channels
S3C2500B IOM2 CONTROLLER 9.3.1 B CHANNELS The B1 and B2 provide two clear 64 Kbit/s user data channels to/from the network. 9.3.2 D CHANNEL The 16 Kbit/s D channel provides a connection between the layer-2 and layer-1 components 9.3.3 MONITOR CHANNELS There are two programming channels, monitors 0 and 1, Each channel has an associated pair of MX and MR handshake bits that control data flow.
Page 418: Channel Operation
9.3.7 CHANNEL OPERATION 9.3.7.1 Monitor channel operation The monitor channel is a handshake protocol for high speed information exchange between S3C2500B and other devices. The monitor channel operates on an asynchronous basis. While data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using MX (monitor transmit) and MR (monitor receive).
Page 419 S3C2500B IOM2 CONTROLLER The monitor protocol is illustrated in figure9-2. Before the data in IOM2MTD register is transmitted, The IOM2 controller should verify that the transmission is idle, that is, MX/MR is inactive ("1") for two or more than 2 frames.
Page 420 S3C2500B 9.3.7.3 Monitor channel collision detection When more than two devices is attached to IOM2-bus, the S3C2500B resolves the collision by waiting inactive in the MX/MR bits before sending and a per bit check on the transmitted data. Monitor channel access priority is determined by the address of the monitor message contained in the first monitor byte transmitted.
Page 421 S3C2500B IOM2 CONTROLLER 9.3.7.5 TIC Bus Access The TIC bus capability enables more than one device to access IOM2 bus. The arbitration mechanism is implemented in the last byte of channel2 of IOM2 interface. This allows external communication controllers (up to 7) to access the C/I0 and D Channel in the channel0 of IOM2 interface.
Page 422 As a result, the actual data pins of the S3C2500B IOM2 interface need to be both inputs and outputs. When the DBREV bit in IOM2CON is set, the DU pin is used to receive downstream data and the DD pin is used to send upstream data.
Page 423: Tsa (Time Slot Assigner)
The S3C2500B includes three time-slot-assigners (TSA), which provide flexible data path control between the three HDLCs and external interfaces. A variety of data interface can be supported by the S3C2500B with the TSA : raw Data Communication Equipment (DCE), Pulse Code Modulation (PCM) highway (non-multiplexed mode and multiplexed mode) and ISDN Oriented Modular Interface (IOM2).
Page 424: Hdlc External Pin Multiplexed Signals
IOM2 CONTROLLER S3C2500B 9.4.3 HDLC EXTERNAL PIN MULTIPLEXED SIGNALS HDLC external pins are multiplexed among the various operating modes. The Mode bits in TSAxCON determines operating mode of each TSA and HDLC external pins are automatically configured according to Mode bits as follows.
Page 425: Iom2 Special Registers
S3C2500B IOM2 CONTROLLER 9.5 IOM2 SPECIAL REGISTERS Table 9-2. IOM2 Special Registers Register Address Description Reset Value IOM2CON 0xF0130000 Control Register 0x00000000 IOM2STAT 0xF0130004 Status Register 0x00000080 IOM2INTEN 0xF0130008 Interrupt Enable Register 0x00000000 IOM2TBA 0xF013000C TIC Bus Address 0x00000007 IOM2ICTD...
Page 426: Iom2Con Register
IOM2 CONTROLLER S3C2500B 9.5.1 IOM2CON REGISTER Table 9-3. IOM2CON Register (Control Register) Register Address Description Reset Value IOM2CON 0xF0130000 Control Register 0x00000000 Bit Number Bit Name Description IOM2 Enable (IOM2EN) 0 = Disable, 1 = Enable Data Bus Reverse (DBREV)
Page 427 S3C2500B IOM2 CONTROLLER 15 14 13 12 11 10 9 8 7 6 [0] IOM2 Enable (IOM2EN) 0 = Disable 1 = Enable [1] Data Bus Reverse (DBREV) 0 = DU: upstream DD: downstream 1 = DU: downstream DD: upstream...
Page 428: Iom2 Status Register
IOM2 CONTROLLER S3C2500B 9.5.2 IOM2 STATUS REGISTER Table 9-4. IOM2STAT Register (Status Register) Register Address Description Reset Value IOM2STAT 0xF0130004 Status Register 0x00000080 Bit Number Bit Name Description C/I0 Channel Buffer Available (CI0BA) 0 = C/I0 receive data is not valid...
Page 429 S3C2500B IOM2 CONTROLLER 13 12 11 10 9 8 7 6 [0] CI 0 Buffer Available (CI0BA) 0 = normal 1 = CI0 buffer available [1] Reserved [2] CI 1 Buffer Available (CI1BA) 0 = Normal 1 = CI1 buffer available...
Page 430: Iom2 Interrupt Enable Register
IOM2 CONTROLLER S3C2500B 9.5.3 IOM2 INTERRUPT ENABLE REGISTER Table 9-5. IOM2INTEN Register (Interrupt Enable Register) Register Address Description Reset Value IOM2INTEN 0xF0130008 Interrupt Enable Register 0x00000000 Bit Number Bit Name Description CI0BAIE C/I0 Channel Buffer Available Interrupt Enable CI1BAIE C/I1 Channel Buffer Available Interrupt Enable...
Page 431 S3C2500B IOM2 CONTROLLER 13 12 11 10 9 8 7 6 [0] CI 0 Buffer Available Interrupt Enable (CI0BAIE) 0 = Disable 1 = Enable [1] Reserved [2] CI 1 Buffer Available Interrupt Enable (CI1BAIE) 0 = Disable 1 = Enable...
Page 432: Iom2 Tic Bus Address Register
IOM2 CONTROLLER S3C2500B 9.5.4 IOM2 TIC BUS ADDRESS REGISTER Table 9-6. IOM2TBA Register (TIC Bus Address Register) Register Address Description Reset Value IOM2TBA 0xF013000C TIC Bus Address 0x00000007 Bit Number Bit Name Description [2:0] TIC Bus Address (TBA) This field defines device-specific address used to gain access to TIC bus for D and C/I0 channel.
Page 433: Iom2 Ic Channel Transmit Data Register
S3C2500B IOM2 CONTROLLER 9.5.5 IOM2 IC CHANNEL TRANSMIT DATA REGISTER Table 9-7. IOM2ICTD (IOM2 IC Channel Transmit Data Register) Register Address Description Reset Value IOM2ICTD 0xF0130010 IC Channel Transmit Data 0x000000FF Bit Number Bit Name Description [7:0] ICTD Transmit Data [31:8] Reserved.
Page 434: Iom2 C/I0 Channel Transmit Data Register
IOM2 CONTROLLER S3C2500B 9.5.6 IOM2 C/I0 CHANNEL TRANSMIT DATA REGISTER Table 9-9. IOM2CITD0 (IOM2 C/I0 Channel Transmit Data Register) Register Address Description Reset Value IOM2CITD0 0xF0130018 C/I0 Channel Transmit Data 0x0000000F Bit Number Bit Name Description [3:0] CITD0 This field includes the data to be transmitted on the C/I0 channel.
Page 435: Iom2 C/I1 Channel Transmit Data Register
S3C2500B IOM2 CONTROLLER 9.5.7 IOM2 C/I1 CHANNEL TRANSMIT DATA REGISTER Table 9-11. IOM2CITD1 (IOM2 C/I1 Channel Transmit Data Register) Register Address Description Reset Value IOM2CITD1 0xF0130020 C/I1 Channel Transmit Data 0x0000003F Bit Number Bit Name Description [5:0] CITD1 This field includes the data to be transmitted on the C/I1 channel.
Page 436: Iom2 Monitor Channel Transmit Data Register
IOM2 CONTROLLER S3C2500B 9.5.9 IOM2 MONITOR CHANNEL TRANSMIT DATA REGISTER Table 9-13. IOM2MTD (IOM2 Monitor Channel Transmit Data Register) Register Address Description Reset Value IOM2MTD 0xF0130028 Monitor Channel Transmit Data 0x000000FF Bit Number Bit Name Description [7:0] MTxD This field includes the data to be transmitted on the monitor channel selected by MSEL if MEN = 1.
Page 437: Tsa A Control Register
S3C2500B IOM2 CONTROLLER 9.5.11 TSA A CONTROL REGISTER Table 9-15. TSAACON (TSA A Control Register) Register Address Description Reset Value TSAACON 0xF0130030 TSA A Control Register 0x00000000 Bit Number Bit Name Description [11:0] START The location of start bit of time slot assigned to HDLCA...
Page 438: Tsa B Control Register
IOM2 CONTROLLER S3C2500B 9.5.12 TSA B CONTROL REGISTER Table 9-16. TSABCON (TSA B Control Register) Register Address Description Reset Value TSABCON 0xF0130034 TSA B Control Register 0x00000000 Bit Number Bit Name Description [11-0] START The location of start bit of time slot assigned to HDLCB...
Page 439: Tsa C Control Register
S3C2500B IOM2 CONTROLLER 9.5.13 TSA C CONTROL REGISTER Table 9-17. TSACCON (TSA C Control Register) Register Address Description Reset Value TSACCON 0xF0130038 TSA C Control Register 0x00000000 Bit Number Bit Name Description [11:0] START The location of start bit of time slot assigned to HDLCC...
Page 440: Iom2Strb (Strobe Register)
IOM2 CONTROLLER S3C2500B 9.5.14 IOM2STRB (STROBE REGISTER) Table 9-18. IOM2STRB (Strobe Register) Register Address Description Reset Value IOM2STRB 0xF013003C Strobe Register 0x00000000 Bit Number Bit Name Description [7:0] START The location of start bit of time slot assigned to STRB...
Page 441: Overview
S3C2500B USB CONTROLLER USB FUNCTION CONTROLLER 10.1 OVERVIEW USB products are easy to use for end users. Electrical details, such as bus termination, are isolated from end users and plug and play is supported. There’re other merits for users; Self identifying peripherals, automatic mapping function to driver, auto configuration, dynamically attach and detach and reconfiguration, and so on.
Page 442: Features
USB CONTROLLER S3C2500B 10.2 FEATURES Important features of the S3C2510 USB block are as follows: • Fully Compliant to USB 1.1 Specification • Supports Only Full Speed Function (12Mbps) • Complete Device Configuration • Compatible with both OpenHCI and Intel UHCI Standards •...
Page 443: Function Descriptions
S3C2500B USB CONTROLLER 10.3 FUNCTION DESCRIPTIONS 10.3.1 USB BUS TOPOLOGY AND PHYSICAL CONNECTION There are two kinds of cable connectors, A type for hub downstream port, and B type for device(or called as function, Node). So end users easily connect cable.
Page 444: Packet Formats
USB CONTROLLER S3C2500B Stereo Audio Low Speed BULK Stereo Audio Low Speed BULK Stereo Audio BULK Stereo Audio BULK Stereo Audio BULK Stereo Audio BULK Stereo Audio BULK Stereo Audio BULK Stereo Audio BULK Stereo Audio BULK Figure 10-2. USB 1.1 Frame Model 10.3.3 PACKET FORMATS...
Page 445: Bit Stuffing And Nrzi Coding
S3C2500B USB CONTROLLER 8 bits 7 bits 4 bits 5 bits ADDR ENDP CRC5 Token (In/Out) 8 bits 0-1023 bytes 16 bits DATA CRC16 Data (Toggle) 8 bits Handshake/Low Speed Preamble 8 bits 11 bits 5 bits Frame Number CRC5 Start of Frame Figure 10-3.
Page 446: Control Transactions
USB CONTROLLER S3C2500B 10.3.6 CONTROL TRANSACTIONS Control transfers are bursty, non-periodic, host software-initiated request/response communication, typically used for command/status operations. Control transfers allow access to different parts of a device. Control transfers are intended to support configuration/command/status type communication flows between client software and its function. A control...
Page 447: Usb Block Descriptions
S3C2500B USB CONTROLLER 10.4 USB BLOCK DESCRIPTIONS 10.4.1 USB BLOCK OVERVIEW USB block is compatible with USB spec 1.1. There're 5 EPs (Endpoint) with EP0 for control transfer. This block uses two input clocks, 133MHz and 48MHz. 133MHz clock is used to special registers access and USB-to-system bus interfacing.
Page 448 USB CONTROLLER S3C2500B fun_bit_stuff VPOUT VMOUT data_in fun_crc fun_sync_detect crc_out nrzi_dec_out fun_dpll fun_shiftreg dpll_rxd nrzi_dec_out dpll_rxd fun_tx_mux tx_mux_out[7:0] tx_mux_out[7:0] TX_DATA fun_eop_detect shiftreg_out[7:0] tx_buf_out[7:0] VPIN VMIN fun_pid_dec RX_DATA[7:0] XRXD shiftreg_out[7:0] syn_VPIN fun_rst_detect VPIN VMIN Figure 10-5. SIE Block Diagram 10-8...
Page 449: Usb Special Registers
S3C2500B USB CONTROLLER 10.5 USB SPECIAL REGISTERS The USB special registers are defined as read-write or read-only or write-only registers according to the direction of information flow. The addresses of these registers are shown in Table 10-1. Table 10-1. USB Registers...
Page 450: Usb Function Address Register
USB CONTROLLER S3C2500B 10.5.1 USB FUNCTION ADDRESS REGISTER This register maintains the USB device address assigned by the host. The MCU writes the value received through a SET_ADDRESS descriptor to this register. This address is used for the next token.
Page 451 S3C2500B USB CONTROLLER [6:0] Function Address Field (FAF) [7] Address UPdate (AUP) [31:8] Reserved Figure 10-6. USBFA Register 10-11...
Page 452: Usb Power Management Register
USB CONTROLLER S3C2500B 10.5.2 USB POWER MANAGEMENT REGISTER This register is used for suspend, resume, reset and data-swapping signaling. The different bits in this register are explained below: Table 10-4. USBPM Register Register Address Description Reset Value USBPM 0xF00E0004 USB power management register 0x00000000 Table 10-5.
Page 453 S3C2500B USB CONTROLLER [0] SUSpend Enable (SUSE) 0 = Suspend mode disable 1 = Suspend mode enable [1] SUSpend Mode (SUSM) 0 = Normal operation 1 = Suspend state [2] ResUme (RU) 0 = Normal or suspend state 1 = Resume signal generation in suspend state...
Page 454: Usb Interrupt Register
USB CONTROLLER S3C2500B 10.5.3 USB INTERRUPT REGISTER There’re five endpoints (EP0 - EP4) Each bit in this register corresponds to the respective endpoint number. All interrupts corresponding to endpoints whose direction is programmable (Mode = IN/OUT), are mapped to this register.
Page 455 S3C2500B USB CONTROLLER Table 10-7. USBINTR Register Description Bit Number Bit Name Description EP0Interrupt This bit corresponds to endpoint 0 interrupt. (EP0I) The USB sets this bit under the following conditions: 1. ORDY bit is set. 2. INRDY bit is cleared.
Page 456 USB CONTROLLER S3C2500B [0] EP0 Interrupt (EP0I) 0 = No EP0 interrupt 1 = EP0 interrupt generated [1] EP1 Interrupt (EP1I) 0 = No EP1 interrupt 1 = EP1 interrupt generated [2] EP2 Interrupt (EP2I) 0 = No EP2 interrupt...
Page 457: Usb Interrupt Enable Register
S3C2500B USB CONTROLLER 10.5.4 USB INTERRUPT ENABLE REGISTER Corresponding to each USB Interrupt Register (USBINTR), there is an interrupt enable bit at USB Interrupt Enable Register (USBINTRE). By default all interrupts are disbled. Table 10-8. USBINTRE Register Register Address Description...
Page 458 USB CONTROLLER S3C2500B 11 10 [0] EndPoint 0 Interrupt ENable (EP0IEN) 0 = Endpoint 0 interrupt disable 1 = Endpoint 0 interrupt enable [1] EndPoint 1 Interrupt ENable (EP1IEN) 0 = Endpoint 1 interrupt disable 1 = Endpoint 1 interrupt enable...
Page 459: Usb Frame Number Register
S3C2500B USB CONTROLLER 10.5.5 USB FRAME NUMBER REGISTER These registers maintain the Frame Number within SOF Packet. Frame Number within SOF Packet are 11bits. Table 10-10. USBFN Register Register Address Description Reset Value USBFN 0xF00E0010 USB Frame Number register 0x00000000 Table 10-11.
Page 460: Usb Disconnect Timer Register
USB CONTROLLER S3C2500B 10.5.6 USB DISCONNECT TIMER REGISTER This register turns USB bus into disconnected state. First, You set the disconnect interval time in the connect register. Next, set the enable bit USBDISCONN[31]. Then, the disconnect logic keeps the line state in SE0(Single Ended Zero).
Page 461 S3C2500B USB CONTROLLER CNTVLE [22:0] CouNT VaLuE (CNTVLE) [23:30] Reserved [31] DISconnet operation STaRT (DISSTRT) 0 = No operation 1 = Both D+/D- go to 0 and all USB registers R/W blocked. Figure 10-11. USBDISCONN Register 10-21...
Page 462: Usb Endpoint 0 Common Status Register
USB CONTROLLER S3C2500B 10.5.7 USB ENDPOINT 0 COMMON STATUS REGISTER This register includes the control bits, status bits, and max packet size value for endpoint 0. Table 10-15. USBEP0CSR Register Register Address Description Reset Value USBEP0CSR 0xF00E0018 USB Endpoint 0 Common Status Register 0x00000001 Table 10-16.
Page 463 S3C2500B USB CONTROLLER Table 10-16. USBEP0CSR Register Description (Continued) Bit Number Bit Name Description [27] Data END The MCU sets this bit: (DEND) 1. After loading the last packet of data into the FIFO, at the same time INRDY is set.
Page 464 USB CONTROLLER S3C2500B 31 30 29 28 27 26 25 24 [3:0] MAXP value (MAXP) [3:0]value x 8 = max packet size [6:4] Reserved [7] MAXP value SETting enable (MAXPSET) 0 = MAXP value isn't changed 1 = MAXP value is changed...
Page 465: Usb Endpoint 1 Common Status Register
S3C2500B USB CONTROLLER 10.5.8 USB ENDPOINT 1 COMMON STATUS REGISTER This register includes the control bits, status bits, IN/OUT status information, and max packet size value for endpoint 1. Table 10-17. USBEP1CSR Register Register Address Description Reset Value USBEP1CSR 0xF00E001C...
Page 466 USB CONTROLLER S3C2500B Table 10-18. USBEP1CSR Register Description (Continued) Bit Number Bit Name Description [12] In mode, AuTo This bit is valid only when endpoint 1 is set to IN. SET (IATSET) If set, whenever the MCU writes MAXP data, IINRDY will be automatically be set without any intervention from MCU.
Page 467 S3C2500B USB CONTROLLER Table 10-18. USBEP1CSR Register Description (Continued) Bit Number Bit Name Description [20] Out mode, This bit is valid only when endpoint 1 is set to OUT. Fifo FLUSH The MCU writes a “1” to flush the FIFO.
Page 468 USB CONTROLLER S3C2500B Table 10-18. USBEP1CSR Register Description (Continued) Bit Number Bit Name Description [26] In mode, UNDER This bit is valid only when endpoint 1 is set to IN run (IUNDER) ISO. The USB sets this bit when in ISO mode, an IN token is received and the IINRDY bit is not set.
Page 469 S3C2500B USB CONTROLLER 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 9 [2:0] MAXP value (MAXP) [19] (OUT) Data ERRor (ODERR) [2:0] value x 8 = max packet size...
Page 470: Usb Endpoint 2 Common Status Register
USB CONTROLLER S3C2500B 10.5.9 USB ENDPOINT 2 COMMON STATUS REGISTER This register includes the control bits, status bits, IN/OUT status information, and max packet size value for endpoint 2. Table 10-19. USBEP2CSR Register Register Address Description Reset Value USBEP2CSR 0xF00E0020...
Page 471 S3C2500B USB CONTROLLER Table 10-20. USBEP2CSR Register Description (Continued) Bit Number Bit Name Description [12] In mode, AuTo This bit is only valid only when endpoint 2 is set to SET (IATSET) If set, whenever the MCU writes MAXP data, IINRDY will be automatically be set without any intervention from MCU.
Page 472 USB CONTROLLER S3C2500B Table 10-20. USBEP2CSR Register Description (Continued) Bit Number Bit Name Description [20] Out mode, This bit is valid only when endpoint 2 is set to OUT. Fifo FLUSH The MCU writes a “1” to flush the FIFO.
Page 473 S3C2500B USB CONTROLLER Table 10-20. USBEP2CSR Register Description (Continued) Bit Number Bit Name Description [27] In mode, Fifo This bit is valid only when endpoint 2 is set to IN. FLUSH (IFFLUSH) The MCU sets this bit if it intends to flush the IN FIFO.
Page 474 USB CONTROLLER S3C2500B 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 9 [2:0] MAXP value (MAXP) [19] (OUT) Data ERRor (ODERR) [2:0]value x 8 = max packet size...
Page 475: Usb Endpoint 3 Common Status Register
S3C2500B USB CONTROLLER 10.5.10 USB ENDPOINT 3 COMMON STATUS REGISTER This register includes the control bits, status bits, IN/OUT status information, and max packet size value for endpoint 3. Table 10-21. USBEP3CSR Register Register Address Description Reset Value USBEP3CSR 0xF00E0024...
Page 476 USB CONTROLLER S3C2500B Table 10-22. USBEP3CSR Register Description (Continued) Bit Number Bit Name Description [12] In mode, AuTo This bit is only valid only when endpoint 3 is set to SET (IATSET) If set, whenever the MCU writes MAXP data, IINRDY will be automatically be set without any intervention from MCU.
Page 477 S3C2500B USB CONTROLLER Table 10-22. USBEP3CSR Register Description (Continued) Bit Number Bit Name Description [20] Out mode, Fifo This bit is valid only when endpoint 3 is set to OUT. FLUSH The MCU writes a “1” to flush the FIFO.
Page 478 USB CONTROLLER S3C2500B Table 10-22. USBEP3CSR Register Description (Continued) Bit Number Bit Name Description [27] In mode, Fifo This bit is valid only when endpoint 3 is set to IN. FLUSH (IFFLUSH) The MCU sets this bit if it intends to flush the IN FIFO.
Page 479 S3C2500B USB CONTROLLER 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 9 [3:0] MAXP value (MAXP) [19] (OUT) Data ERRor (ODERR) [3:0]value x 8 = max packet size...
Page 480: Usb Endpoint 4 Common Status Register
USB CONTROLLER S3C2500B 10.5.11 USB ENDPOINT 4 COMMON STATUS REGISTER This register includes the control bits, status bits, IN/OUT status information, and max packet size value for endpoint 4. Table 10-23. USBEP4CSR Register Register Address Description Reset Value USBEP4CSR 0xF00E0028...
Page 481 S3C2500B USB CONTROLLER Table 10-24. USBEP4CSR Register Description (Continued) Bit Number Bit Name Description [12] In mode, AuTo This bit is only valid only when endpoint 4 is set to SET (IATSET) If set, whenever the MCU writes MAXP data, IINRDY will be automatically be set without any intervention from MCU.
Page 482 USB CONTROLLER S3C2500B Table 10-24. USBEP4CSR Register Description (Continued) Bit Number Bit Name Description [21] Out mode, This bit is valid only when endpoint 4 is set to OUT. SenD STALL The MCU writes a “1” to this bit to issue a STALL (OSDSTALL) handshake to the USB.
Page 483 S3C2500B USB CONTROLLER Table 10-24. USBEP4CSR Register Description (Continued) Bit Number Bit Name Description [27] In mode, Fifo This bit is valid only when endpoint 4 is set to IN. FLUSH (IFFLUSH) The MCU sets this bit if it intends to flush the IN FIFO.
Page 484 USB CONTROLLER S3C2500B 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 9 [3:0] MAXP value (MAXP) [19] (OUT) Data ERRor (ODERR) [3:0]value x 8 = max packet size...
Page 485: Usb Write Count For Endpoint 0 Register
S3C2500B USB CONTROLLER 10.5.12 USB WRITE COUNT FOR ENDPOINT 0 REGISTER When OORDY is set for OUT endpoints, USBWCEP0[22:16] maintains the byte-count number of data in FIFO due to be unloaded by the MCU. In case of IN mode, MCU first writes the byte-count number of data to be loaded into FIFO, then write data into FIFO.
Page 486 USB CONTROLLER S3C2500B 16 15 WRTCNT CPUWRTCNT [6:0] ep0 CPU WRiTe CouNT (CPUWRTCNT) [15:7] Reserved [22:16] ep0 WRiTe CouNT (WRTCNT) [31:23] Reserved Figure 10-17. USBWCEP0 Register 10-46...
Page 487: Usb Write Count For Endpoint 1 Register
S3C2500B USB CONTROLLER 10.5.13 USB WRITE COUNT FOR ENDPOINT 1 REGISTER When OORDY is set for OUT endpoints, USBWCEP1[21:16] maintains the byte-count number of data in FIFO due to be unloaded by the MCU. In case of IN mode, MCU first writes the byte-count number of data to be loaded into FIFO, then write data into FIFO.
Page 488 USB CONTROLLER S3C2500B WRTCNT CPUWRTCNT [5:0] ep1 CPU WRiTe CouNT (CPUWRTCNT) [15:6] Reserved [21:16] ep1 WRiTe CouNT (WRTCNT) [31:22] Reserved Figure 10-18. USBWCEP1 Register 10-48...
Page 489: Usb Write Count For Endpoint 2 Register
S3C2500B USB CONTROLLER 10.5.14 USB WRITE COUNT FOR ENDPOINT 2 REGISTER When OORDY is set for OUT endpoints, USBWCEP2[21:16] maintains the byte-count number of data in FIFO due to be unloaded by the MCU. In case of IN mode, MCU first writes the byte-count number of data to be loaded into FIFO, then write data into FIFO.
Page 490 USB CONTROLLER S3C2500B WRTCNT CPUWRTCNT [5:0] ep2 CPU WRiTe CouNT (CPUWRTCNT) [15:6] Reserved [21:16] ep2 WRiTe CouNT (WRTCNT) [31:22] Reserved Figure 10-19. USBWCEP2 Register 10-50...
Page 491: Usb Write Count For Endpoint 3 Register
S3C2500B USB CONTROLLER 10.5.15 USB WRITE COUNT FOR ENDPOINT 3 REGISTER When OORDY is set for OUT endpoints, USBWCEP3[22:16] maintains the byte-count number of data in FIFO due to be unloaded by the MCU. In case of IN mode, MCU first writes the byte-count number of data to be loaded into FIFO, then write data into FIFO.
Page 492 USB CONTROLLER S3C2500B WRTCNT CPUWRTCNT [6:0] ep3 CPU WRiTe CouNT (CPUWRTCNT) [15:7] Reserved [22:16] ep3 WRiTe CouNT (WRTCNT) [31:23] Reserved Figure 10-20. USBWCEP3 Register 10-52...
Page 493: Usb Write Count For Endpoint 4 Register
S3C2500B USB CONTROLLER 10.5.16 USB WRITE COUNT FOR ENDPOINT 4 REGISTER When OORDY is set for OUT endpoints, USBWCEP4[22:16] maintains the byte-count number of data in FIFO due to be unloaded by the MCU. In case of IN mode, MCU first writes the byte-count number of data to be loaded into FIFO, then write data into FIFO.
Page 494 USB CONTROLLER S3C2500B WRTCNT CPUWRTCNT [6:0] ep4 CPU WRiTe CouNT (CPUWRTCNT) [15:7] Reserved [22:16] ep4 WRiTe CouNT (WRTCNT) [31:23] Reserved Figure 10-21. USBWCEP4 Register 10-54...
Page 495: Usb Endpoint 0/1/2/3/4 Fifo Register
S3C2500B USB CONTROLLER 10.5.17 USB ENDPOINT 0/1/2/3/4 FIFO REGISTER Each endpoint has his own FIFO. To access to each FIFO data, User must use these registers. Table 10-35. USBEP0/ 1/ 2/ 3/ 4 Descriptions Register Address Description Reset Value USBEP0...
Page 496 USB CONTROLLER S3C2500B EP0 FIFO [31:0] EndPoint 0 data FIFO EP1 FIFO [31:0] EndPoint 1 data FIFO EP2 FIFO [31:0] EndPoint 2 data FIFO EP3 FIFO [31:0] EndPoint 3 data FIFO EP4 FIFO [31:0] EndPoint 4 data FIFO Figure 10-22. USBEP0/1/2/3/4 FIFO Registers...
Page 497: Overview
The Data Encryption Standard (DES) consists of the Data Encryption Algorithm (DES) and Triple Data Encryption Algorithm (TDEA, as described in ANSI X9.52). The DES/3DES accelerator of the S3C2500B is designed in such a way that they may be used in a computer system or network to provide cryptographic protection to binary coded data.
Page 498 DES/3DES S3C2500B DES/3DES PWDATA keygen key48 key1 PADDR Register write sig. key2 PENABLE key3 decode PSELx Control in_mode (state left side data sig. machine) PWRITE Status Status PWDATA des_mode left side data desctrl sbox Interrupt wr_indata PRDATA enable in_mode (state left side data sig.
Page 499: Des/3Des Special Registers
S3C2500B DES/3DES 11.3 DES/3DES SPECIAL REGISTERS Table 11-1. DES/3DES Special Registers Overview Registers Address Description Reset Value DESCON 0xF0090000 DES/3DES control register 0×00000000 0x00000231 DESSTA 0xF0090004 DES/3DES status register 0x00000000 DESINT 0xF0090008 DES/3DES interrupt enable register 0x00000000 DESRUN 0xF009000C DES/3DES run enable register...
Page 500: Des/3Des Control Register
DES/3DES S3C2500B 11.3.1 DES/3DES CONTROL REGISTER Table 11-2. DES/3DES Control Register Description Bit Number Bit Name Description Run Enable 0 = DES/3DES disable 1 = DES/3DES enable This bit is the same register as the Run Enable bit of the Run Enable Register.
Page 501: Des/3Des Status Register
S3C2500B DES/3DES 11.3.2 DES/3DES STATUS REGISTER Table 11-3. DES/3DES Status Register Description Bit Number Bit Name Description Idle This bit indicates whether DES/3DES is running or not [3:1] Reserved These bits have 0 value. Available DESINFIFO DESINFIFO is vacant 4(or 2, depends on DESCON[7]) words or more, this bit is set to 1.
Page 502: Des/3Des Run Enable Register
DES/3DES S3C2500B 11.3.4 DES/3DES RUN ENABLE REGISTER Table 11-5. DES/3DES Run Enable Register Description Bit Number Bit Name Description Run Enable If you set this bit to 1, DES/3DES engine begin to run. This bit is the same register as the Run Enable bit of the DES/3DES Control Register.
Page 503 S3C2500B DES/3DES If users need to byte-swapped key value, they can control it by using DESCON[12]. If DESCON[12] is set, byte-swapped key is written to DESKEY2R. Otherwise, original key is written to DESKEY2R. 11-7...
Page 504: Des/3Des Key 3 Left Side Register
DES/3DES S3C2500B 11.3.7 DES/3DES KEY 3 LEFT SIDE REGISTER Table 11-10. DES/3DES Key 3 Left Side Register Description Bit Number Bit Name Description [1:32] Key 3 Left Half The left half of the Key3 should be stored to this register. The 8 of each byte is parity bit, and it isn't used for encryption/decryption.
Page 505: Des/3Des Input/Output Data Fifo Register
S3C2500B DES/3DES 11.3.9 DES/3DES INPUT/OUTPUT DATA FIFO REGISTER Table 11-14. DES/3DES Input Data FIFO Description Bit Number Bit Name Description [31:0] DESINFIFO This FIFO can be filled by CPU or DMA (depends on control register value). This FIFO consists of 8 words. If data are transferred by DMA the 4-word burst transaction (DESCON[7] is zero, and DCON#[5] is one) is recommended.
Page 506: Des/3Des Operation
DES/3DES S3C2500B 11.4 DES/3DES OPERATION The 64-bit data to be encoded should be written to DESINFIFO of DES/3DES block by CPU or DMA. When the data conversion is completed, the Valid DESOUTFIFO bit in DESSTA is set to 1 and the CPU/DMA can read the encrypted data from the DESOUTFIFO.
Page 507: Performance Calculation Guide
S3C2500B DES/3DES 11.5 PERFORMANCE CALCULATION GUIDE Supposed condition: — DESINFIFO has already data to be encrypting. — DESOUTFIFO can be written data to be encrypted. Cycle Unit (Reference Figure 11-1 DES/3DES Block Diagram) Unit 1: from DESINFIFO to input buffer (1+1/2 cycle)
Page 508: Overview
S3C2500B GDMA CONTROLLER GDMA CONTROLLER 12.1 OVERVIEW The S3C2500B has a six-channel General DMA controller, called the GDMA. The six-channel GDMA performs the following data transfers without CPU intervention: • Memory-to-Memory (Memory to/from Memory, Memory to/from USB) • External Device-to-Memory (External Device to/from Memory) •...
Page 509 GDMA CONTROLLER S3C2500B AHB BUS Mode Selection GDMA Channel 0 xGDMA_Req0 HUART0 GDMA_Req GDMA_Ack xGDMA_Ack0 Mode Selection Port 18 Data GDMA Channel 1 xGDMA_Req1 IOPCON1[18] HUART0 GDMA_Req GDMA_Ack xGDMA_Ack1 Mode Selection Port 19 Data GDMA Channel 2 xGDMA_Req2 IOPCON1[19] HUART0...
Page 510: Gdma Special Registers
S3C2500B GDMA CONTROLLER 12.3 GDMA SPECIAL REGISTERS Table 12-1. GDMA Special Registers Overview Registers Address Description Reset Value × DPRIC 0xF0051000 GDMA priority configuration register 00000000 DPRIF 0xF0052000 GDMA programmable priority register for fixed 0x00543210 DPRIR 0xF0053000 GDMA programmable priority register for round-robin 0x00000000 ×...
Page 511: Gdma Programmable Priority Registers
GDMA CONTROLLER S3C2500B 12.3.1 GDMA PROGRAMMABLE PRIORITY REGISTERS The GDMA can support the fixed priority and the round-robin priority for the local arbitration of six GDMA channels by register setting. Especially, the GDMA can program the priority order in the fixed priority mode as well as the ratio of the bus occupancy in the round-robin priority mode.
Page 512 S3C2500B GDMA CONTROLLER DPRIC [0] Priority configuration 0 = Round-robin 1 = Fixed priority DPRIF 12 11 16 15 Reserved dprif5 dprif4 dprif3 dprif2 dprif1 dprif0 Low Priority High Priority DPRIR 16 15 12 11 Reserved dprir5 dprir4 dprir3 dprir2...
Page 513 When DPRIR is 0x0 and only GDMA channel 0, 1, and 2 are used, the expected bus occupancy for each channel is 1/3. However, S3C2500B does not work in that way, instead, GDMA channel 0 gets 4/6 of the bus occupancy, GDMA 1 1/6, and GDMA 2 1/6.
Page 514 S3C2500B GDMA CONTROLLER The following is the problem solving with software. 1. Method 1 DPRIR Channel Expected Real DPRIR Channel Occupancy System Bus Occupancy Occupancy GDMA 0 GDMA 0 GDMA 1 GDMA 1 ⇒ GDMA 2 GDMA 2 Problem Problem Solving by Method 1 Writing "0x000330", instead of "0x0"...
Page 515 GDMA CONTROLLER S3C2500B GDMA Channel Needed Recommended Problem Solving Recommended GDMA Channel Used when S/W 2 Method 2 0, 1, 2, 3, 4, or 5 Method 2 0/3 or 1/4 or 2/5 Method 2 0/2/4 or 1/3/5 Method 1 Method 1...
Page 516: Gdma Control Registers
This bit determines the number of external GDMA requests (xGDMA_Req 0-3) that are required for a GDMA operation. In Single mode, when [4] = "0", the S3C2500B requires an external GDMA request for every GDMA operation. In Block mode, when [4] = "1", the S3C2500B requires only one external GDMA request...
Page 517 GDMA CONTROLLER S3C2500B Table 12-4. GDMA Control Register Description (Continued) Bit Number Bit Name Description Transfer size [7:6] These bits determine the transfer data width to be one byte, one half-word, or one word. If you select a byte transfer operation, the source/destination address will be increased or decreased by one with each transfer.
Page 518 S3C2500B GDMA CONTROLLER 13 12 11 10 9 8 7 6 5 4 3 RESERVED [0] Run enable (RE) 0 = Disable GDMA operation 1 = Enable GDMA operation [3:1] Mode selection (MODE) 000 = Software mode (Memory to Memory, or Momory to/from USB)
Page 519: Gdma Source/Destination Address Registers
0, 1, 2, 3, 4, and 5. These address registers cover the whole external memory space, including the special purpose registers. You have to reference the memory map of the S3C2500B (Chapter 4) when you want to set these address registers. Depending on the settings you make to the GDMA control register (DCON), the source or destination addresses will either remain the same, or they will be increased or decreased.
Page 520: Gdma Transfer Count Registers
S3C2500B GDMA CONTROLLER 12.3.4 GDMA TRANSFER COUNT REGISTERS The GDMA transfer count register indicates the byte transfer rate, which runs at 24-bit, on GDMA channels 0, 1, 2, 3, 4 and 5. Whenever GDMA transfer count register transmits the data of GDMA, it will be diminished by transfer width. In other words, when transfer size (TS) is byte, it will be diminished at 1, in the case of half-word at 2 and word at 4.
Page 521: Gdma Run Enable Registers
GDMA CONTROLLER S3C2500B 12.3.5 GDMA RUN ENABLE REGISTERS The GDMA run enable register (DRER) can enable or disable the RUN ENABLE bit, DCON[0] of the GDMA control register (DCON). The DRER register is write-only register. Table 12-7. DRER0/1/2/3/4/5 Registers Registers...
Page 522: Gdma Interrupt Pending Register
S3C2500B GDMA CONTROLLER 12.3.6 GDMA INTERRUPT PENDING REGISTER The GDMA interrupt pending register (DIPR) indicates the pending state of GDMA interrupt by the pending bit [0] of the DIPR register. The DIPR[0] is active high. The DIPR[0] can be asserted after the GDMA operation completes successfully when the Interrupt Enable field of DCON[12] is "1".
Page 523: Gdma Mode Operation
The block mode can be used only with the external GDMA request mode. 12.4.3 HUART MODE S3C2500B has two HUARTs. GDMA channel 0,1,2 can transmit the data of HUART0. GDMA channel 3,4,5 can transmit the data of HUART1. If GDMA mode selection bit [3:1] to “010” or “011”, GDMA gets ready to communicate with HUART.
Page 524: Des Mode
12.4.4 DES MODE S3C2500B has only one DES. Any channel of GDMA can transmit the data of DES. If GDMA mode selection bit "100" or "101", GDMA gets ready to communicate with DES. If GDMA mode is "100" (DES IN mode) and GDMA receives the request signal transmitted from DES, GDMA transfers IN data of DES in memory into IN buffer/FIFO of DES.
Page 525: Data Transfer Modes
GDMA CONTROLLER S3C2500B 12.5.3 DATA TRANSFER MODES 12.5.3.1 Single Mode A GDMA request (xGDMA_Req or an internal request) causes one byte, one half-word, or one word to be transmitted if four-data burst mode is disabled, or four times of transfer size if four-data burst mode is enabled.
Page 526: Gdma Transfer Timing Data
Figure 12-10 provides the detailed timing data for GDMA data transfers that are triggered by external GDMA requests. Please note that read/write timing depends on which memory banks are selected. The S3C2500B has the internal clock, HCLK, as the operating clock. The clock frequency of HCLK is 133MHz,...
Page 527: Single And One Data Burst Mode
GDMA CONTROLLER S3C2500B 12.6.1 SINGLE AND ONE DATA BURST MODE (DCON[3:1] = 001, [4] = 0, [5] = 0) xGDMA_Req and xGDMA_Ack signals are active high. Recommand deasserted time HCLK xGDMA_Req xGDMA_Ack source dest. Address addr addr source dest. Data...
Page 528: Single And Four Data Burst Mode
S3C2500B GDMA CONTROLLER 12.6.2 SINGLE AND FOUR DATA BURST MODE (DCON[3:1] = 001, [4] = 0, [5] = 1) xGDMA_Req & xGDMA_Ack signals are active high. In four data burst mode, GDMA transfers four data and GDMA Transfer Count Register (DTCR) value decreases by four.
Page 529: Block And One Data Burst Mode
GDMA CONTROLLER S3C2500B 12.6.3 BLOCK AND ONE DATA BURST MODE (DCON[3:1] = 001, [4] = 1, [5] = 0) xGDMA_Req and xGDMA_Ack signals are active high. GDMA transfers data from single xGDMA_Req signal till GDMA Transfer Count Register (DTCR) consumes to 0.
Page 530: Block And Four Data Burst
S3C2500B GDMA CONTROLLER 12.6.4 BLOCK AND FOUR DATA BURST (DCON[3:1] = 001, [4] = 1, [5] = 1) This timing diagram is the same with block and one data burst, except that it is four data burst. Recommand deasserted time...
Page 531 GDMA CONTROLLER S3C2500B NOTES 12-24...
Page 532: Serial I/O (Console Uart)
SERIAL I/O (CONSOLE UART) 13.1 OVERVIEW The S3C2500B Console UART (Universal Asynchronous Receiver/Transmitter) unit provides one independent asynchronous serial I/O (SIO) port. The port can operate in interrupt-based mode. That is, the Console UART can generate internal interrupts to transfer data between the CPU and the serial I/O port.
Page 533 SERIAL I/O (CONSOLE UART) S3C2500B Transmit Data Register (CUTXBUF) Baud Rate Divisor Transmit Shift Register CUTXD IR TX Baud Rate Generator Encoder UART Control Register (CUCON) UART Interrupt Enable (CUINT) UART Status Register (CUSTAT) Control Character1,2 (CUCHAR1,2) Receive Data Register...
Page 534: Console Uart Special Registers
S3C2500B SERIAL I/O (CONSOLE UART) 13.3 CONSOLE UART SPECIAL REGISTERS Table 13-1. Console UART Special Registers Overview Register Address Description Size Reset Value CUCON 0xF0060000 Console UART control register 0x00000000 CUSTAT 0xF0060004 Console UART status register 0x00060800 CUINT 0xF0060008 Console UART interrupt enable register...
Page 535: Console Uart Control Registers
SERIAL I/O (CONSOLE UART) S3C2500B 13.3.1 CONSOLE UART CONTROL REGISTERS Table 13-2. CUCON Registers Register Address Description Size Reset Value CUCON 0xF0060000 Console UART control register 0x00000000 Table 13-3. Console UART Control Register Description Bit Number Bit Name Description [1:0]...
Page 536 11 = 8-bit [14] Infra-red mode (IR) The S3C2500B Console UART block supports infra-red (IR) transmit and receive operations. In IR mode, the transmit period is pulsed at a rate of 3/16 that of the normal serial transmit rate (when the transmit data value in the CUTXBUF register is zero).
Page 537 SERIAL I/O (CONSOLE UART) S3C2500B 30 29 28 27 26 25 23 22 20 19 18 17 16 15 14 13 12 11 8 7 6 [1:0] SIO transmit mode selection (TMODE) 00 = Disable 01 = CPU request 10 = Reserved...
Page 538 S3C2500B SERIAL I/O (CONSOLE UART) 30 29 28 26 25 23 22 20 19 18 17 16 15 14 13 12 11 8 7 6 [28:15] Reserved (This bit should be cleared) [29] Software Flow Control Enable (SFEN) 0 = Disable Software Flow Control...
Page 539: Console Uart Status Registers
SERIAL I/O (CONSOLE UART) S3C2500B 13.3.2 CONSOLE UART STATUS REGISTERS Table 13-4. CUSTAT Registers Register Address Description Size Reset Value CUSTAT 0xF0060004 Console UART status register 0x00060800 Table 13-5. Console UART Status Register Description Bit Number Bit Name Description Receive Data Valid...
Page 540 S3C2500B SERIAL I/O (CONSOLE UART) Table 13-5. Console UART Status Register Description (Continued) Bit Number Bit Name Description Overrun Error (OER) This bit is automatically set to '1' whenever an overrun error occurs during a serial data receiving operation. When CURXBUF has a previous valid data and a new received data is going to be written into CURXBUF, CUSTAT[4] is set to '1'.
Page 541 SERIAL I/O (CONSOLE UART) S3C2500B 18 17 16 12 11 [0] Receive Data Valid (RDV) 0 = No valid data (Receive FIFO top or CURXBUF) 1 = Valid data present (Receive FIFO top or CURXBUF) [1] Break Signal Deteced (BKD)
Page 542: Console Uart Interrupt Enable Register
S3C2500B SERIAL I/O (CONSOLE UART) 13.3.3 CONSOLE UART INTERRUPT ENABLE REGISTER Table 13-6. CUINT Registers Register Address Description Size Reset Value CUINT 0xF0060008 Console UART interrupt enable register 0x00000000 Table 13-7. Console UART Interrupt Enable Register Description Bit Number Bit Name...
Page 543 SERIAL I/O (CONSOLE UART) S3C2500B 19 18 17 16 [0] Receive Data Valid Interrupt Enable (RDVIE) [1] Break Signal Detected Interrupt Enable (BKDIE) [2] Frame Error Interrupt Enable (FERIE) [3] Parity Error Interrupt Enable (PERIE) [4] Overrun Error Interrupt Enable (OERIE)
Page 544: Uart Transmit Data Register
S3C2500B SERIAL I/O (CONSOLE UART) 13.3.4 UART TRANSMIT DATA REGISTER Table 13-8. CUTXBUF Registers Register Address Description Size Reset Value CUTXBUF 0xF006000C Console UART transmit data register – Table 13-9. Console UART Transmit Register Description Bit Number Bit Name Description...
Page 545: Uart Receive Data Register
SERIAL I/O (CONSOLE UART) S3C2500B 13.3.5 UART RECEIVE DATA REGISTER Table 13-10. CURXBUF Registers Register Address Description Size Reset Value CURXBUF 0xF0060010 Console UART receive data register – Table 13-11. Console UART Receive Register Description Bit Number Bit Name Description...
Page 546: Uart Baud Rate Divisor Register
S3C2500B SERIAL I/O (CONSOLE UART) 13.3.6 UART BAUD RATE DIVISOR REGISTER The values stored in the baud rate divisor registers, CUBRD, let you determine the serial TX/RX clock rate (baud rate) as follows: PCLK2 or EXT_UCLK BRGOUT = (CNT0+1) × 16 ×...
Page 547: Console Uart Baud Rate Examples
SERIAL I/O (CONSOLE UART) S3C2500B 13.3.7 CONSOLE UART BAUD RATE EXAMPLES If the system clock frequency is 133 MHz and PCLK2 is selected, the maximum BRGOUT output clock rate is PCLK2/16 (= 4,156,250 Hz). EXT_UCLK is the external clock input pin for Console UART. PCLK2 and EXT_UCLK can be selected by CUCON[5] register.
Page 548: Uart Control Character Register 1 And 2
S3C2500B SERIAL I/O (CONSOLE UART) 13.3.8 UART CONTROL CHARACTER REGISTER 1 AND 2 These Control Character registers can be used for Software Flow control. In Software Flow Control mode, you should write control characters into these registers. Any character in these registers can be used as a software control flow character and you can use maximum 8 characters for it.
Page 549 SERIAL I/O (CONSOLE UART) S3C2500B <TRANSMIT> Stop Start Data Bits (5-8) Parity Start CUTXD (1-2) INT_TXD <RECEIVE> Stop Start Data Bits (5-8) Parity Start Data Bits CURXD (1-2) INT_RXD Receive Data Receive Data CURXBUF Figure 13-12. Interrupt-Based Serial I/O Transmit and Receive Timing Diagram...
Page 550 S3C2500B SERIAL I/O (CONSOLE UART) SIO Frame Start Stop Data Bits Figure 13-13. Serial I/O Frame Timing Diagram (Normal Console UART) IR Transmit Frame Start Stop Data Bits 3/16T 7/16T 6/16T Bit frame = T Figure 13-14. Infra-Red Transmit Mode Frame Timing Diagram...
Page 551 SERIAL I/O (CONSOLE UART) S3C2500B IR Receive Frame Start Stop Data Bits 3/16T Bit frame = T 13/16T Figure 13-15. Infra-Red Receive Mode Frame Timing Diagram 13-20...
Page 552: Overview
FIFO, instead of Tx/Rx buffer register(HUTXBUF/HURXBUF). They are controlled by each FIFO trigger level. The SIO control units provide software controls for mode selection, and for status and interrupt generation. In S3C2500B, software flow control or hardware flow control can be selected according to the application. 14-1...
Page 553 SERIAL I/O (HIGH-SPEED UART) S3C2500B Modem Control Signal Transmit Data TxBuffer Register Transmit Control -------------- Transmit FIFO Transmit Status (32 Bytes) HUART Transmit Shift TX pin Control Register IR Tx Encoder Status Receive Data Block RxBuffer Register Receive Control --------------...
Page 554: High-Speed Uart Special Registers
S3C2500B SERIAL I/O (HIGH-SPEED UART) 14.3 HIGH-SPEED UART SPECIAL REGISTERS Table 14-1. High-Speed UART 0 Special Registers Overview Register Address Description Size Reset Value HUCON 0xF0070000 High-Speed UART control register 0x00000000 HUSTAT 0xF0070004 High-Speed UART status register – HUINT 0xF0070008...
Page 555: High-Speed Uart Control Registers
SERIAL I/O (HIGH-SPEED UART) S3C2500B 14.3.1 HIGH-SPEED UART CONTROL REGISTERS Table 14-3. High-Speed UART Control Registers Registers Address Description Reset Value HUCON 0xF0070000 High-Speed UART control register 0x00000000 0xF0080000 Table 14-4. High-Speed UART Control Register Description Bit Number Bit Name...
Page 556 Reserved This bit should be cleared by zero. [16] Transmit FIFO enable S3C2500B High-Speed UART block support 32 byte FIFO. If this bit (TFEN) set to one, transmit data moved to Tx FIFO and then sent. [17] Receive FIFO enable S3C2500B High-Speed UART block support 32 byte FIFO.
Page 557 SERIAL I/O (HIGH-SPEED UART) S3C2500B Table 14-4. High-Speed UART Control Register Description (Continued) Bit Number Bit Name Description Receive FIFO trigger This two bit trigger level value determines when the receiver start to level (RFTL) move the received data in 32-byte receive FIFO.
Page 558 S3C2500B SERIAL I/O (HIGH-SPEED UART) 30 29 28 27 26 25 23 22 20 19 18 17 16 15 14 13 12 11 8 7 6 [1:0] SIO transmit mode selection (TMODE) 00 = Disable 01 = Interrupt request 10 = GDMA request...
Page 559 SERIAL I/O (HIGH-SPEED UART) S3C2500B 30 29 28 27 26 25 23 22 20 19 18 17 16 15 14 13 12 11 8 7 6 [16] Transmit FIFO Enable (TFEN) 0 = Disable Transmit FIFO 1 = Enable Transmit FIFO...
Page 560: High-Speed Uart Status Registers
S3C2500B SERIAL I/O (HIGH-SPEED UART) 14.3.2 HIGH-SPEED UART STATUS REGISTERS Table 14-5. High-Speed UART Status Registers Registers Offset Address Description Reset Value HUSTAT 0xF0070004 High-Speed UART status register – 0xF0080004 Table 14-6. High-Speed UART Status Register Description Bit Number Bit Name...
Page 561 SERIAL I/O (HIGH-SPEED UART) S3C2500B Table 14-6. High-Speed UART Status Register Description (Continued) Bit Number Bit Name Description Overrun Error (OER) This bit automatically set to "1" whenever an overrun error occurs during a serial data receiving operation. When HURXBUF has a...
Page 562 S3C2500B SERIAL I/O (HIGH-SPEED UART) Table 14-6. High-Speed UART Status Register Description (Continued) Bit Number Bit Name Description [12] Receive Event time out During Receive FIFO mode, if there is a valid data in URXFIFO or Receive FIFO within a promised time internal which is determined (E_RxTO) according to WL(Word Length) , this bit is set to '1' .
Page 563 SERIAL I/O (HIGH-SPEED UART) S3C2500B 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 [0] Receive Data Valid (RDV) 0 = No valid data (Receive FIFO-top or HURXBUF) 1 = Valid data present (Receive FIFO-top or HURXBUF)
Page 564 S3C2500B SERIAL I/O (HIGH-SPEED UART) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 [12] Receive Event Time out (E_RxTO) 0 = A promised time is not elapsed during receiving. 1 = Valid data in a promised time...
Page 565: High-Speed Uart Interrupt Enable Register
SERIAL I/O (HIGH-SPEED UART) S3C2500B 14.3.3 HIGH-SPEED UART INTERRUPT ENABLE REGISTER Table 14-7. HUCON Interrupt Enable Registers Registers Offset Address Description Reset Value HUINT 0xF0070008 High-Speed UART Interrupt Enable register 0x00 0xF0080008 Table 14-8. High-Speed UART Interrupt Enable Register Description...
Page 566 S3C2500B SERIAL I/O (HIGH-SPEED UART) 18 17 16 13 12 11 10 9 8 7 6 [0] Receive Data Valid Interrupt Enable (RDVIE) [1] Break Signal Detected Interrupt Enable (BKDIE) [2] Frame Error Interrupt Enable (FERIE) [3] Parity Error Interrupt Enable (PERIE)
Page 567: High-Speed Uart Transmit Buffer Register
14.3.4 HIGH-SPEED UART TRANSMIT BUFFER REGISTER S3C2500B has a 32-byte Transmit FIFO, and the bottom of FIFO is HUTXBUF. All data to be transmitted are stored into this register at first in FIFO mode, if next buffer has invalid data, then shifted to next buffer. But in non-FIFO mode, a new data to transmit will be moved from HUTXBUF to Tx shift register.
Page 568: High-Speed Uart Receive Buffer Register
14.3.5 HIGH-SPEED UART RECEIVE BUFFER REGISTER S3C2500B has a 32-byte Receive FIFO, and the bottom of FIFO is HURXBUF. All data to be received are stored in this register at first in FIFO mode, if next buffer has invalid data, then shifted to next buffer. But in non-FIFO mode, a new received data will be moved to HURXBUF.
Page 569: High-Speed Uart Baud Rate Divisor Register
SERIAL I/O (HIGH-SPEED UART) S3C2500B 14.3.6 HIGH-SPEED UART BAUD RATE DIVISOR REGISTER The values stored in the baud rate divisor registers, HUBRD let you determine the serial Tx/Rx clock rate (baud rate) as follows: PCLK2 or EXT_UCLK BRGOUT = (CNT0+1) × 16 ×...
Page 570: High-Speed Uart Baud Rate Examples
S3C2500B SERIAL I/O (HIGH-SPEED UART) 14.3.7 HIGH-SPEED UART BAUD RATE EXAMPLES High-Speed UART BRG input clock, PCLK2 is the system clock frequency divided by 2. If the system clock frequency is 133 MHz and PCLK2 is selected, the maximum BRGOUT output clock rate is PCLK2/16 (= 4,156,250 Hz).
Page 571: High-Speed Uart Control Character 1 Register
SERIAL I/O (HIGH-SPEED UART) S3C2500B 14.3.8 HIGH-SPEED UART CONTROL CHARACTER 1 REGISTER This Control Character registers can be used for Software Flow control. In Software Flow Control mode, you should write control characters into this registers. If not, the reset value will be used as control character. For example, even if you want to use one control character, all control characters will have same value with it.
Page 572: High-Speed Uart Control Character 2 Register
S3C2500B SERIAL I/O (HIGH-SPEED UART) 14.3.9 HIGH-SPEED UART CONTROL CHARACTER 2 REGISTER This Control Character registers can be used for Software Flow control. In Software Flow Control mode, you should write control characters into this registers. If not, the reset value will be used as control character. For example, even if you want to use one control character, all control characters will have same value with it.
Page 573: High-Speed Uart Autoband Boundary Register
SERIAL I/O (HIGH-SPEED UART) S3C2500B 14.3.10 HIGH-SPEED UART AUTOBAND BOUNDARY REGISTER This autoband boundary register limit range of each baud rate value that is auto-detected. ABB0 is the lowest boundary value (high baud rate) and ABB3 is the highest value (low baud rate) of autobaud boundary register (actually the highest boundary value is ABT3).
Page 574: High-Speed Uart Autobaud Table Regsiter
S3C2500B SERIAL I/O (HIGH-SPEED UART) 14.3.11 HIGH-SPEED UART AUTOBAUD TABLE REGSITER This autobaud table register corrects each baud rate divisor value that is auto-detected. For detail refer figure 14- 15. If high-speed UART uses external UCLK (29.4912 MHz) and you want to use 460800 baud rate, though high- speed UART detects baud rate divisor register value (CNT0, CNT1) as 0x04, autobaud mechanism will correct baud rate divisor register value as 0x03, because detected value is between 0x05 (ABB1) and 0x02 (ABB0).
Page 575: High-Speed Uart Operation
SERIAL I/O (HIGH-SPEED UART) S3C2500B 14.4 HIGH-SPEED UART OPERATION Data Transmit Operation Flow: If there is no data at Tx Buffer FIFO of High-Speed UART (in case of FIFO, if data in the Tx FIFO are empty as same amount of trigger level), High-Speed UART generates interrupt or GDMA request signal. It depends on High-Speed UART mode.
Page 576 S3C2500B SERIAL I/O (HIGH-SPEED UART) Data Size Start Bit Figure 14-15. When Signal is Asserted During Transmit Operation Data Region Start Bit Stop Bit Figure 14-16. When CTS Signal is De-asserted During Transmit Operation 14-25...
Page 577: Software Flow Control
SERIAL I/O (HIGH-SPEED UART) S3C2500B Data Region Start Bit Stop Bit Figure 14-17. Normal Received Rx Data Data Region Start Bit Stop Bit Pin Signal Internal Start Bit Signal Figure 14-18. DCD Lost During Rx Data Receive 14.4.3 SOFTWARE FLOW CONTROL Software can control High-Speed UART by control characters.
Page 578 S3C2500B SERIAL I/O (HIGH-SPEED UART) <TRANSMIT> Stop Start Data Bits (5-8) Parity Start TX DATA (1-2) INT_TXD <RECEIVE> Stop Start Data Bits (5-8) Parity Start Data Bits RX DATA (1-2) INT_RXD Receive Data Receive Data HURXBUF Figure 14-19. Interrupt-Based Serial I/O Transmit and Receive Timing Diagram...
Page 579 SERIAL I/O (HIGH-SPEED UART) S3C2500B <TRANSMITTER> TMODE Select DMA Mode Stop TX DATA Start Data Bits (5-8) Parity (1-2) uart_tx_req uart_tx_ack Figure 14-20. DMA-Based Serial I/O Timing Diagram (Tx Only) < RECEIVER > RMODE Select DMA Mode Stop RX DATA...
Page 580 S3C2500B SERIAL I/O (HIGH-SPEED UART) SIO Frame Start Stop Data Bits Figure 14-22. Serial I/O Frame Timing Diagram (Normal High-Speed UART) IR Transmit Frame Start Stop Data Bits 3/16T 7/16T 6/16T Bit frame = T Figure 14-23. Infra-Red Transmit Mode Frame Timing Diagram...
Page 581 SERIAL I/O (HIGH-SPEED UART) S3C2500B IR Transmit Frame Start Stop Data Bits 3/16T Bit frame = T 13/16T Figure 14-24. Infra-Red Receive Mode Frame Timing Diagram 14-30...
Page 582: Overview
I/O PORTS 15.1 OVERVIEW S3C2500B has 64 programmable I/O ports. I/O port function control registers (IOPCON2: upper word, IOPCON1: lower word) select either function's port or GPIO. If IOPCON1/2 register is set to GPIO, IOPMODE1/2 register should be set to either input mode or output mode.
Page 583: I/O Port Special Register
I/O PORTS S3C2500B 15.3 I/O PORT SPECIAL REGISTER Table 15-1. I/O Port Special Registers Register Address Description Reset Value IOPMODE1 0xF0030000 I/O port mode select register for Port 0 to 31 0xF003FFFF IOPMODE2 0xF0030004 I/O port mode select register for Port 32 to 63...
Page 584 S3C2500B I/O PORTS IOPMODE1 X X X X X IOPMODE2 X X X X X IOPMODE1 IOPMODE2 Signal port Reset value Signal port Reset value GPIO[31] GPIO[63] GPIO[30] GPIO[62] GPIO[29] GPIO[61] GPIO[28] GPIO[60] GPIO[27] GPIO[59] GPIO[26] GPIO[58] GPIO[25] GPIO[57] GPIO[24]...
Page 585: I/O Port Function Control Register
I/O PORTS S3C2500B 15.3.2 I/O PORT FUNCTION CONTROL REGISTER (IOPCON1/2) The I/O port function select registers, IOPCON1/2, are used for function select. IOPCON1/2 are used to configure external interrupt signals, GDMA Req/Ack signals, timer signals, UART Tx/Rx signals, and HDLC Tx/Rx signals.
Page 586 S3C2500B I/O PORTS Reserved IOPCON1 IOPCON1 Default signal Multiplexed signals (0 / 1) default value High speed UART nDSR0 (HUARTnDSR0)/GPIO[31] HUARTnDSR0 High speed UART nDTR0 (HUARTnDTR0)/GPIO[30] HUARTnDTR0 HUARTTXD0 High speed UART RTXD0 (HUARTRTXD0)/GPIO[29] High speed UART RXD0 (HUARTRXD0)/GPIO[28] HUARTRXD0 Timer Output(TOUT)[5] / GPIO[27]...
Page 587 I/O PORTS S3C2500B X X X X X IOPCON2 IOPCON2 Multiplexed signals (0 / 1) Default signal default value HDLC ch.2 TXC(HTXC2) / GPIO[63] HTXC2 HDLC ch.2 RXC(HRXC2) / GPIO[62] HRXC2 HDLC ch.2 nDCD(HnDCD2) / GPIO[61] HnDCD2 HDLC ch.2 nCTS(HnCTS2) / GPIO[60] HnCTS2 HDLC ch.2 nRTS(HnRTS2) / GPIO[59]...
Page 588: I/O Port Control Register For Gdma
S3C2500B I/O PORTS 15.3.3 I/O PORT CONTROL REGISTER FOR GDMA (IOPGDMA) If the port is used for a function's port such as an external GDMA Req/Ack signal, its signal function is determined by the IOPGDMA register. IOPGDMA register is used to configure GDMA Req/Ack signal. I/O ports provide 3-tap filtering, and you can select filtering on or off.
Page 589: I/O Port Control Register For External Interrupt
I/O PORTS S3C2500B 15.3.4 I/O PORT CONTROL REGISTER FOR EXTERNAL INTERRUPT (IOPEXTINT) If the port is used for a function's port such as an external interrupt request, its signal function is determined by the IOPEXTINT register. IOPEXTINT register is used to configure external interrupt request signals. I/O ports provide 3-tap filtering, and you can select filtering on or off.
Page 590 S3C2500B I/O PORTS IOPEXTINT Reserved [23:20] Control external interrupt request5 input for port 13 (xINT5) [23] 0 = active low 1 = active high [22] 0 = filtering off 1 = filtering on [21:20] 00 = level detection 01 = rising edge detection...
Page 591: I/O Port External Interrupt Clear Register
I/O PORTS S3C2500B 15.3.5 I/O PORT EXTERNAL INTERRUPT CLEAR REGISTER (IOPEXTINTPND) External interrupt clear register (IOPEXTINTPND) is set when external interrupt is generated, and you can clear the interrupt status by writing the IOPEXTINTPND status register to '1'. Table 15-6. IOPEXTINTPND Register...
Page 592: I/O Port Data Register
S3C2500B I/O PORTS 15.3.6 I/O PORT DATA REGISTER (IOPDATA1/2) The I/O port data registers, IOPDATA1/2, contain one-bit read values for I/O ports that are configured to input mode and one-bit write values for ports that are configured to output mode.
Page 593 I/O PORTS S3C2500B NOTES 15-12...
Page 594: Overview
INTERRUPT CONTROLLER 16.1 OVERVIEW The S3C2500B interrupt controller has a total of 39 interrupt sources. Interrupt requests can be generated by internal function blocks or external pins. The ARM940T core recognizes two kinds of interrupts: a normal interrupt request (IRQ) and a fast interrupt request (FIQ).
Page 595: Interrupt Sources
INTERRUPT CONTROLLER S3C2500B 16.3 INTERRUPT SOURCES The 39 interrupt sources in the S3C2500B interrupt structure are listed, in brief, as follows: Table 16-1. S3C2500B Internal Interrupt Sources Index Values Interrupt Sources [31] Watchdog Timer interrupt [30] 32-bit Timer 5 interrupt...
Page 596: Interrupt Controller Special Registers
S3C2500B INTERRUPT CONTROLLER Table 16-2. S3C2500B External Interrupt Sources Index Values Interrupt Sources IOM2 interrupt External interrupt 5 External interrupt 4 External interrupt 3 External interrupt 2 External interrupt 1 External interrupt 0 16.4 INTERRUPT CONTROLLER SPECIAL REGISTERS 16.4.1 INTERRUPT MODE REGISTERS Bit settings in the interrupt mode registers, INTMOD and EXTMOD, specify if an interrupt is to be serviced as a fast interrupt (FIQ) or a normal interrupt (IRQ).
Page 597 INTERRUPT CONTROLLER S3C2500B INTMOD [31:0] Internal interrupt mode bits NOTE: Each of the 32 bits in the interrupt mode enable register, INTMOD, corresponds to an interrupt source. When the source interrupt mode bit is set to 1, the interrupt is processed by the ARM940T core in FIQ (fast interrupt) mode.
Page 598: Interrupt Mask Registers
S3C2500B INTERRUPT CONTROLLER EXTMOD [6:0] External interrupt mode bits NOTE: Each of the 7 bits in the external interrupt mode enable register, EXTMOD, corresponds to an external interrupt source. When the source interrupt mode bit is set to 1, the interrupt is processed by the ARM940T core in FIQ (fast interrupt) mode.
Page 599 INTERRUPT CONTROLLER S3C2500B INTMASK [31:0] Individual internal interrupt mask bits NOTE: Each of the 32 bits in the interrupt mask register, INTMASK, corresponds to an interrupt source. When a source interrupt mask bit is 1, the interrupt is not serviced by the ARM940T when the corresponding interrupt request is generated.
Page 600 S3C2500B INTERRUPT CONTROLLER EXTMASK [6:0] Individual external interrupt mask bits NOTE: Each of the 7 bits in the external interrupt mask register, EXTMASK, (except for the global mask bit, G) corresponds to an external interrupt source. When a source interrupt mask bit is 1, the interrupt is not serviced by the ARM940T when the corresponding interrupt request is generated.
Page 601: Interrupt Priority Registers
INTERRUPT CONTROLLER S3C2500B 16.4.3 INTERRUPT PRIORITY REGISTERS The interrupt priority registers, INTPRIOR0–INTPRIOR9, contain information about which interrupt source is assigned to the pre-defined interrupt priority field. Each INTPRIORn register value determines the priority of the corresponding interrupt source. The lowest priority value is 0x0, and the highest priority value is 0x26.
Page 602: Interrupt Offset Register
S3C2500B INTERRUPT CONTROLLER 16.4.4 INTERRUPT OFFSET REGISTER The interrupt offset registers, INTOFFSET_FIQ and INTOFFSET_IRQ, contain the interrupt offset address of the interrupt, which has the highest priority among the pending interrupts. The content of the interrupt offset address is "index value of the interrupt source”.
Page 603 INTERRUPT CONTROLLER S3C2500B Table 16-7. Index Value of Interrupt Sources Index Value Type of Interrupt Sources Returned Default Offset Value (Hex) [38] Watchdog Timer interrupt 0 x 26 [37] 32-bit Timer 5 interrupt 0 x 25 [36] 32-bit Timer 4 interrupt...
Page 604 S3C2500B INTERRUPT CONTROLLER Table 16-7. Index Value of Interrupt Sources (Continued) Index Value Type of Interrupt Sources Returned Default Offset Value (Hex) HUART 0 RX interrupt 0 x 9 HUART 0 TX interrupt 0 x 8 IIC interrupt 0 x 7...
Page 605: Interrupt By Priority Register
INTERRUPT CONTROLLER S3C2500B 16.4.5 INTERRUPT BY PRIORITY REGISTER The interrupt by priority registers, IPRIORHI and IPRIORLO, contain interrupt pending bits, which are re-ordered by the INTPRIORn register settings. IPRIORLO[14] is mapped to the interrupt source of whichever bit index is written into the priority 14 field of the INTPRIORn registers.
Page 606: Overview
S3C2500B 32-BIT TIMERS 32-BIT TIMERS 17.1 OVERVIEW The timer has six 32-bit timers and one watchdog timer. Six 32-bit timers have Timer Mode register (TMOD) which is used to control the operation of the six 32-bit timers, Timer Data registers (TDATAn) which are data registers for counting, Timer Counts registers (TCNTn) which are count value registers, and Timer Interrupt Clear register (TIC) which is used to clear the current interrupt.
Page 607: Interval Mode Operation
32-BIT TIMERS S3C2500B 17.3 INTERVAL MODE OPERATION In interval mode, a timer generates one-shot pulse of preset timer clock duration whenever a time-out occurs. This pulse generates a time-out interrupt that is directly output at the timer's configured output pin (TOUTn). In...
Page 608: Timer Operation Guidelines
32-BIT TIMERS 17.5 TIMER OPERATION GUIDELINES The block diagram in Figure 17-2 shows how the 32-bit timers are configured in the S3C2500B. The following guidelines apply to the timer functions. When a timer is enabled, it loads a data value (TDATA) to its count register (TCNT) and begins decrement of the count register value (TCNT).
Page 609: Timer Special Register
32-BIT TIMERS S3C2500B 17.6 TIMER SPECIAL REGISTER 17.6.1 TIMER MODE REGISTER The timer mode register, TMOD, is used to control the operation of the six 32-bit timers. TMOD register settings are described in Figure 17-3. Table 17-1. TMOD Register Register...
Page 610 S3C2500B 32-BIT TIMERS [0] Timer 0 enable (TE0) [9] Timer 3 enable (TE3) 0 = Disable timer 0 0 = Disable timer 3 1 = Enable timer 0 1 = Enable timer 3 [1] Timer 0 mode selection (TMD0) [10] Timer 3 mode selection (TMD3)
Page 611: Timer Data Registers
32-BIT TIMERS S3C2500B 17.6.2 TIMER DATA REGISTERS The timer data registers, TDATA0 - TDATA5, contain a value that specifies the time-out duration for each timer. The formula for calculating the time-out duration is: (Timer data) cycles. The timer is dependent on the system bus clock. When the system bus is 133 MHz, the minimum value, 0x1 for TDATA, generates interrupt at every 7.5n sec.
Page 612: Timer Count Registers
S3C2500B 32-BIT TIMERS 17.6.3 TIMER COUNT REGISTERS The timer count registers, TCNT0 - TCNT5, contain the current timer 0 - 5 count value, respectively, during the normal operation. Table 17-3. TCNT0 - TCNT5 Registers Register Address Description Reset Value TCNT0...
Page 613: Timer Interrupt Clear Registers
32-BIT TIMERS S3C2500B 17.6.4 TIMER INTERRUPT CLEAR REGISTERS Timer Interrupt Clear register (TIC) clears the current interrupt of the six 32-bit timers and one watchdog timer. Table 17-4. Timer Interrupt Clear Registers Register Address Description Reset Value 0xF0040004 Timer Interrupt Clear...
Page 614: Watchdog Timer Register
S3C2500B 32-BIT TIMERS 17.6.5 WATCHDOG TIMER REGISTER (WDT) To use Watchdog Timer, Watchdog Timer Register (WDT) must be set. If WDT[29] (RST) is ‘1’ when WDT[31] (EN) was asserted, the timeout counter in watchdog timer is cleared as ‘0’. Following this cycle, WDT[29] (RST) is automatically de-asserted.
Page 615 32-BIT TIMERS S3C2500B Table 17-6. Watchdog Timer Timeout Value (WDTVAL, X: Don't Care) (When watchdog timer operates at 133 MHz) Count (N x 7.5ns) No Operation (3.8us) (30.7us) (245.8us) (491.5us) (983.0us) (1.97ms) (3.93ms) (7.86ms) (15.72ms) (31.45ms) (62.91ms) (125.82ms) (251.65ms) (503.31ms) (1.00s)
Page 616: Overview
S3C2500B ELECTRICAL DATA ELECTRICAL DATA 18.1 OVERVIEW This chapter describes the S3C2500B electrical data. 18.2 ABSOLUTE MAXIMUM RATINGS Table 18-1. Absolute Maximum Ratings Symbol Parameter Rating Unit DC supply voltage 1.8V V 3.3V V DC input voltage 3.3V input buffer DC output voltage 3.3V input buffer...
Page 617: Dc Electrical Specifications
ELECTRICAL DATA S3C2500B 18.4 DC ELECTRICAL SPECIFICATIONS Table 18-3. D.C Electric Characteristics = 3.3 V ± 5%, T = -40 to 85 °C Symbol PARAMETER Condition Type Unit High level input voltage LVCMOS interface – – Low level input voltage LVCMOS interface –...
Page 618 S3C2500B ELECTRICAL DATA Table 18-3. D.C Electric Characteristics (Continued) Symbol PARAMETER Condition Type Unit Low level output voltage = 1 µA Type B1 to B12 – – 0.05 = 1 mA Type B1 = 2 mA Type B2 = 4 mA...
Page 619: Max Power Consumption
2. SMDK2500 Evaluation Board (Rev 1.0) without LCD module. HCLKout damping resister (R146) = 48Ω. 3. Clock Mode: Async 166MHz/133MHz 4. Samsung Diagnostic Test: All Test (Remap Mode, I-Cache On, D-Cache On) 5. Samsung Diagnostic Test: Idle (Remap Mode, I-Cache On, D-Cache) Table 18-4.
Page 620: Ac Electrical Characteristics
S3C2500B ELECTRICAL DATA 18.6 AC ELECTRICAL CHARACTERISTICS Table 18-4. Operating Frequency Characteristic Units Core frequency System bus frequency USB Frequency Table 18-5. Clock AC timing specification Characteristic Units µs Internal PLL lock time – Frequency of operation (XCLK) – XCLK cycle time –...
Page 621 ELECTRICAL DATA S3C2500B Table 18-6. AC Electrical Characteristics for S3C2500B Signal Name Description Unit tnRCSd ROM/SRAM chip select delay time 1.32 3.43 tnRCSh ROM/SRAM chip select hold time 1.17 3.02 tnOEd ROM/SRAM output enable delay time 0.79 1.93 tnOEh ROM/SRAM output enable hold time 0.69...
Page 622: Overview
S3C2500B MECHANICAL DATA MECHANICAL DATA 19.1 OVERVIEW The S3C2500B is available in a 272-pin BGA package (272-BGA-2727-AN). 19-1...
Page 623 MECHANICAL DATA S3C2500B ± 0.10 27.00 ± 0.10 24.00 A1 Corner 272-BGA-2727-AN 0.15 MAX 1.27 272-φ 0.76 ± 0.015 φ 0.38 MAX A1 Corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 19-1.

Samsung S3C2500B User Manual

Chapter 1 Product Overview

Chapter 2 Programmer's Model

Chapter 3 Instruction Set

Chapter 4 System Configuration

Chapter 5 Memory Controller

Chapter 6 I 2 C Controller

Chapter 7 Ethernet Controller

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