Multi-Master Iic-Bus Line Control(Iiclc) Register - Samsung S3C2416 User Manual

IIC-BUS INTERFACE

2.5 MULTI-MASTER IIC-BUS LINE CONTROL(IICLC) REGISTER

Register
IICLC0 0x54000010
IICLC0
Bit
IICLC1
Filter enable [2]
SDA output [1:0]
delay
17-14
Address R/W
R/W IIC0-Bus multi-master line control register
IIC-bus filter enable bit.
When SDA port is operating as input, this bit should be High. This
filter can prevent from occurred error by a glitch during double of
PCLK time.
0 = Filter disable
1 = Filter enable
IIC-Bus SDA line delay length selection bits.
SDA line is delayed as following clock time(PCLK)
00 = 0 clocks
01 = 5 clocks
10 = 10 clocks
11 = 15 clocks
S3C2416X RISC MICROPROCESSOR
Description
Description
Reset Value
0x00
Initial State
0
00