Normal Interrupt Status Enable Register - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR

5.20 NORMAL INTERRUPT STATUS ENABLE REGISTER

Setting to 1 enables Interrupt Status.
Register
NORINTSTSEN0
NORINTSTSEN1
Name
ENSTAFIA3
ENSTAFIA2
ENSTAFIA1
ENSTAFIA0
ENSTARWAIT
ENSTACCS
ENSTACARDINT
ENSTACARDREM
Address R/W
0X4AC00034 R/W
0X4A800034 R/W
Bit
Fixed to 0
[15]
The Host Driver shall control error interrupts using the Error
Interrupt Status Enable register. (RO)
FIFO SD Address Pointer Interrupt 3 Status Enable
[14]
1 = Enabled
0 = Masked
FIFO SD Address Pointer Interrupt 2 Status Enable
[13]
1 = Enabled
0 = Masked
FIFO SD Address Pointer Interrupt 1 Status Enable
[12]
1 = Enabled
0 = Masked
FIFO SD Address Pointer Interrupt 0 Status Enable
[11]
1 = Enabled
0 = Masked
Read Wait interrupt status enable
[10]
1 = Enabled
0 = Masked
CCS Interrupt Status Enable
[9]
1 = Enabled
0 = Masked
Card Interrupt Status Enable
If this bit is set to 0, the Host Controller shall clear interrupt
request to the System. The Card Interrupt detection is
stopped when this bit is cleared and restarted when this bit is
set to 1. The Host Driver should clear the Card Interrupt
[8]
Status Enable before servicing the Card Interrupt and
should set this bit again after all interrupt requests from the
card are cleared to prevent inadvertent interrupts.
1 = Enabled
0 = Masked
Card Removal Status Enable
[7]
1 = Enabled
0 = Masked
Description
Normal Interrupt Status Enable Register
(Channel 0)
Normal Interrupt Status Enable Register
(Channel 1)
Description
HSMMC CONTROLLER
Reset Value
0x0
0x0
Initial Value
0
0
0
0
0
0
0
0
0
20-53