Dram Timing Diagram - Samsung S3C2416 User Manual

MOBILE DRAM CONTROLLER S3C2416X RISC MICROPROCESSOR
3.2.3 Supported Programmable Timing Parameters
Figure 6-5. DRAM Timing Diagram
Figure 6-5 shows a timing diagram of DRAM. There are many timing parameters provided by DRAM. And
DRAMC only provides some timing parameters to support various DRAM memories, like SDR, mobile DDR and
DDR2.
tARFC and tRP are programmable, so you can also control the tRAS period by using these parameters. And the
delay from RAS to CAS is determined by tRCD. And CL(CAS Latency) is also programmable. The timing diagram
of CL (CAS Latency) is like Figure 6-6.
Figure 6-6. CL (CAS Latency) Timing Diagram
6-6