Samsung S3C2416 User Manual page 411

S3C2416X RISC MICROPROCESSOR
5.1.3 FIFO Interrupt Control Register (FIFO_INTC_REG)
Register
FIFO_INTC_REG 0x4D408008
Field
Reserved
FIFO_INT_LEVEL
5.1.4 Interrupt Pending Register (INTC_PEND_REG)
Register
INTC_PEND_REG
Field
Reserved
Reserved
INTP_CMD_FIN
INTP_ALL_FIN
INTP_FULL
Reserved
INTP_FIFO_LEVEL
Address R/W
R/W FIFO Interrupt Control
Bit
[31:6]
−
[5:0] If FIFO_INT_E (in INTEN_REG) is set, when FIFO_USED (in
FIFO_STAT_REG) is greater or equal to FIFO_INT_LEVEL, an
interrupt occurs.
Address R/W
0x4D40800C R/W
Bit
[31] Should be set '1'
[30:11] Reserved
[10] Current Command Finished interrupt flag.
Writing '1' to this bit clears this flag.
[9] All Commands Finished interrupt flag.
Writing '1' to this bit clears this flag.
[8] Command FIFO Full interrupt flag.
Writing '1' to this bit clears this flag.
[7:1]
−
[0] FIFO_USED reaches FIFO_INT_LEVEL interrupt flag.
Writing '1' to this bit clears this flag.
Description
Description
Description
Interrupt Pending Register
Description
2D
Reset Value
0x18
Initial State
0x0
0x18
Reset Value
0x0
Initial State
−
−
−
−
−
−
−
18-17