Samsung S3C2416 User Manual page 13

Chapter 16
1 Overview ................................................................................................................................................... 16-1
1.1 Feature ............................................................................................................................................ 16-1
2 Block Diagram........................................................................................................................................... 16-2
3 To Activate USB Port1 for USB 2.0 Function ........................................................................................... 16-3
4 SIE (Serial Interface Engine) .................................................................................................................... 16-4
5 UPH (Universal Protocol Handler) ............................................................................................................ 16-4
6 UTMI (USB 2.0 Transceiver Macrocell Interface)..................................................................................... 16-4
7 USB 2.0 Function Controller Special Registers........................................................................................ 16-5
8 Registers ................................................................................................................................................... 16-7
8.1 Index Register (IR) .......................................................................................................................... 16-7
8.2 Endpoint Interrupt Register (EIR) .................................................................................................... 16-8
8.3 Endpoint Interrupt Enable Register (EIER) ..................................................................................... 16-9
8.4 Function Address Register (FAR) ................................................................................................... 16-10
8.5 ENdpoint Direction Register (EDR) ................................................................................................. 16-11
8.6 Test Register (TR) ........................................................................................................................... 16-12
8.7 System Status Register (SSR) ........................................................................................................ 16-13
8.8 System Control Register (SCR) ...................................................................................................... 16-15
8.9 EP0 Status Register (EP0SR)......................................................................................................... 16-16
8.10 EP0 Control Register (EP0CR) ..................................................................................................... 16-17
8.11 Endpoint# Buffer Register (EP#BR) ............................................................................................. 16-18
8.12 Endpoint Status Register (ESR).................................................................................................... 16-19
8.13 Endpoint Control Register (ECR) .................................................................................................. 16-21
8.14 Byte read Count Register (BRCR) ................................................................................................ 16-22
8.15 Byte Write Count Register (BWCR) .............................................................................................. 16-23
8.16 MAX Packet Register (MPR)......................................................................................................... 16-24
8.17 DMA Control Register (DCR) ........................................................................................................ 16-25
8.18 DMA Transfer Counter Register (DTCR) ...................................................................................... 16-26
8.19 DMA FIFO Counter Register (DFCR) ........................................................................................... 16-27
8.20 DMA Total Transfer Counter Register 1/2 (DTTCR 1/2)............................................................... 16-28
8.21 DMA Interface Control Register (DICR) ........................................................................................ 16-29
8.22 Memory Base Address Register (MBAR)...................................................................................... 16-30
8.23 Memory Current Address Register (MCAR).................................................................................. 16-31
8.24 Burst FIFO Control Register(FCON) ............................................................................................. 16-31
8.25 Burst FIFO Status Register(FSTAT) ............................................................................................. 16-31
8.26 AHB Master(DMA) Operation Flow Chart ..................................................................................... 16-32
S3C2416X RISC MICROPROCESSOR
Table of Contents
USB 2.0 Function
(Continued)
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