Main Data Area Ecc0 Status Register - Samsung S3C2416 User Manual

NAND FLASH CONTROLLER
13.12

MAIN DATA AREA ECC0 STATUS REGISTER

Register Address
NFMECC0 0x4E000034
NFMECC1 0x4E000038
13.12.1 When ECCType is 1-bit ECC
NFMECC0
MECC0_3
MECC0_2
MECC0_1
MECC0_0
NFMECC1
Reserved
NOTE: The NAND flash controller generate NFMECC when read or write main area data while the MainECCLock
(NFCONT[7]) bit is '0'(Unlock).
13.12.2 When ECCType is 4-bit ECC.
NFMECC0 Bit
th
[31:24]
4 Parity
rd
[23:16]
3 Parity
nd
[15:8]
2 Parity
st
[7:0]
1 Parity
NFMECC1 Bit
Reserved [31:24]
th [23:16]
7 Parity
th [15:8]
6 Parity
th [7:0]
5 Parity
NOTE: The NAND flash controller generate these ECC parity codes when write main area data while the MainECCLock
(NFCONT[7]) bit is '0' (unlock).
7-24
R/W
R NAND Flash ECC status register
R NAND Flash ECC status register
Bit
[31:24] ECC3 for data[7:0]
[23:16] ECC2 for data[7:0]
[15:8] ECC1 for data[7:0]
[7:0] ECC0 for data[7:0]
Bit
[31:0] Reserved
th
4 Check Parity generated from main area
rd
3 Check Parity generated from main area
nd
2 Check Parity generated from main area
st
1 Check Parity generated from main area
Reserved
th
7 Check Parity generated from main area
th
6 Check Parity generated from main area
th
5 Check Parity generated from main area
Description
Description
Description
Description
Description
S3C2416 RISC MICROPROCESSOR
Reset Value
0xXXXXXX
0xXXXXXX
Initial State
Initial State
0x00000000
Initial State
Initial State
0xXX
0xXX
0xXX
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00