Samsung S3C2416 User Manual page 199

S3C2416X RISC MICROPROCESSOR
DCONn Bit
Reserved [26:2
5]
PADDRFIX [24]
Reserved [23]
RELOAD [22]
DSZ [21:2
0]
TC [19:0]
transfer (single or burst of length four) DMA stops and waits for
another DMA request.
1 = Whole service mode is selected in which one request gets
atomic transfers to be repeated until the transfer count reaches to
0. In this mode, additional request is not required. Here, note that
even in the whole service mode, DMA releases the bus after each
atomic transfer and then tries to re-get the bus to prevent starving
of other bus masters.
Reserved for future use
APB Address fix control
0 = Increment
1 = Fix
If you want to fix the APB address during burst operation, set this bit
to 1.
Reserved for future use
Set the reload on/off option.
0 = Auto reload is performed when a current value of transfer count
becomes 0 (i.e., all the required transfers are performed).
1 = DMA channel (DMA REQ) is turned off when a current value of
transfer count becomes 0. The channel on/off bit(DMASKTRIGn[1])
is set to 0(DREQ off) to prevent unintended further start of new
DMA operation
Data size to be transferred.
00 = Byte
01 = Half word
10 = Word
11 = Reserved
Initial transfer count (or transfer beat).
Note that the actual number of bytes that are transferred is
computed by the following equation: DSZ x TSZ x TC, where DSZ,
TSZ, and TC represent data size (DCONn[21:20]), transfer size
(DCONn[28]), and initial transfer count, respectively.
This value will be loaded into CURR_TC only if the CURR_TC is 0
and the DMA ACK is 1.
Description
DMA CONTROLLER
Initial State
00
0
0
0
00
00000
8-13