Samsung S3C2416 User Manual page 108

SYSTEM CONTROLLER
The special clocks are controlled by SCLKCON register. Some blocks in the device require several operating
frequencies, i.e., 48 MHz and 24 MHz for USB interface block. Thus, these output frequencies can be controlled
by the CLKDIV values.
SCLKCON
RESERVED
SPICLK_MPLL0
RESERVED
PCM0_EXT
DDRCLK(Hx2CLK)
SSMCCLK(HX1_2CLK)
SPICLK_0
HSMMCCLK_EXT
HSMMCCLK_1
RESERVED
DISPCLK
I2SCLK_0
UARTCLK
RESERVED
HSMMCCLK_0
RESERVED
USB HOST
RESERVED
2-30
Bit
[31:20] -
[19] Enable SPICLK0 (MPLL)
[18] -
[17] Enable PCM0 External Clock
[16] Enable DDRCLK
[15] Enable SSMCCLK
[14] Enable HS-SPI_0 (EPLL) clock
Enable HSMMC_EXT clock for HSMMC0, 1 (EXTCLK)
[13]
Reference clock of MPLL
Enable HSMMC1_1 clock for
[12]
(from EPLL or USB48M output)
[11] -
[10] Enable display controller clock
[9] Enable I2S_0 clock
[8] Enable UART clock
[7] -
Enable HSMMC_0 clock for
[6]
(from EPLL or USB48M output)
[5:2] -
[1] Enable USB HOST clock
[0] -
S3C2416X RISC MICROPROCESSOR
Description
Initial
Value
0xFFF
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0xF
1
1