Samsung S3C2416 User Manual page 493

S3C2416X RISC MICROPROCESSOR
Name
STACARDREM
STACARDINS
STABUFRDRDY
STABUFWTRDY
Bit
detect the Card Interrupt without SD Clock to support wakeup. In
4-bit mode, the card interrupt signal is sampled during the interrupt
cycle, so there are some sample delays between the interrupt
signal from the SD card and the interrupt to the Host System. It is
necessary to define how to handle this delay.
When this status has been set and the Host Driver needs to start
this interrupt service, Card Interrupt Status Enable in the Normal
Interrupt Status Enable register shall be set to 0 in order to clear
the card interrupt statuses latched in the Host Controller and to
stop driving the interrupt signal to the Host System. After
completion of the card interrupt service (It should reset interrupt
factors in the SD card and the interrupt signal may not be
asserted), set Card Interrupt Status Enable to 1 and start
sampling the interrupt signal again. (ROC, RW1C)
1 = Generate Card Interrupt
0 = No Card Interrupt
[7]
Card Removal
This status is set if the Card Inserted in the Present State register
changes from 1 to 0. When the Host Driver writes this bit to 1 to
clear this status, the status of the Card Inserted in the Present
State register should be confirmed. Because the card detect state
may possibly be changed when the Host Driver clear this bit and
interrupt event may not be generated. (RW1C)
1 = Card removed
0 = Card state stable or Debouncing
[6]
Card Insertion
This status is set if the Card Inserted in the Present State register
changes from 0 to 1. When the Host Driver writes this bit to 1 to
clear this status, the status of the Card Inserted in the Present
State register should be confirmed. Because the card detect state
may possibly be changed when the Host Driver clear this bit and
interrupt event may not be generated. (RW1C)
1 = Card inserted
0 = Card state stable or Debouncing
[5]
Buffer Read Ready
This status is set if the Buffer Read Enable changes from 0 to 1.
Refer to the Buffer Read Enable in the Present State register.
(RW1C)
1 = Ready to read buffer
0 = Not ready to read buffer
[4]
Buffer Write Ready
This status is set if the Buffer Write Enable changes from 0 to 1.
Refer to the Buffer Write Enable in the Present State register.
(RW1C)
1 = Ready to write buffer
0 = Not ready to write buffer
Description
HSMMC CONTROLLER
Initial Value
0
0
0
0
20-47